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agilent HFCT-701XBD, 10 gb ethernet, 1310 nm, 10 km 10gbase-lr, xenpak lan-phy data sheet features ieee std 802.3ae type 10gbase- lr pmd (10 gigabit ethernet standard) compliant with xenpak msa draft 3.0 standard sc duplex fiber optic connector standard 70 pin electrical connector four wide xaui electrical interface mdio management interface only 3.3 v and 1.8 v supplies required (compatible with the xenpak aps) 5 diagnostic loopback modes front panel hot pluggable excellent thermal and emi integrity performance supports high port densities hot plug power up circuit removes psu sequence dependency and reduces inrush current precision onboard oscillator - no external clocks required applications enterprise to metro uplinks campus trunking data aggregation exchange point-to-point links description the HFCT-701XBD is an intelligent optical module which incorporates the complete physical layer functionality from the 10.3125 gb/s 64b/66b encoded optical interface to a xaui compliant (4 channel x 3.125 gb/s) 8b/ 10b encoded electrical interface and vice versa. the control interface (mdio) is also integrated. the HFCT-701XBD module includes a transmitter that incorporates an uncooled, directly modulated 1310 nm dfb laser. the receiver subassembly includes a highly reliable pin photodiode. the mux/demux, xaui interface and mdio management functions are all integrated into the module, as is a precision oscillator that removes any need for an external reference clock.
2 table of contents general specifications general optical specifications 3 general electrical specifications 3 environmental specifications 3 technical specifications absolute maximum ratings 4 recommended operating conditions 4 optical specifications 5 electrical control and sense i/o parameters 6 electrical mdio parameters 6 lectrical high speed i/o parameters 7 electrical eye mask 8 general i/o pin summary 9 electrical pin out 10 mechanical specifications 13 functional descriptions block diagram 18 transmitter path summary 18 receiver path summary 19 management data input output (mdio) interface 19 eeprom interface 10 monitor and diagnostic features 22 loopbacks 25 reset operation 25 internal clock functionality 27 qfct-7096 registers qfct-7096 device 1 pma/pmd registers 29 qfct-7096 device 3 pcs registers 43 qfct-7096 device 4 phyxs registers 49 digital optical monitoring (dom) overview 54 regulatory compliance electrostatic discharge (esd) 64 electromagnetic interference (emi) 64 immunity 64 glossary 64
3 general specifications figure 1. high level block diagram general optical specifications optical connector: sc duplex optical line rate: 10.3125 gb/s link length: 10 km, with g.652 fiber laser: 1310 nm, directly modulated, uncooled dfb detector: pin diode electrical connector system control agilent HFCT-701XBD 8b/10b 3.125 x 4 serdes mac with rs other signals 8b/10b 3.125 x 4 serdes 64b/66b 10g serdes mdio opto opto optical connectors general electrical specifications connector: 70-pin, mates to tyco/amp part no. 1367337-1 or equivalent supply voltages: +1.8v and +3.3v e->o coding (transmit direction): 8b/10b coding removed, 64b/ 66b added o->e coding (receive direction): 64b/66b removed, 8b/10b coding added xaui interface: 100 w differential, ac- coupled i/o on tx and rx, per ieee802.3ae clause 47 control interface: mdio, 1.2 v, per ieee802.3ae clause 45.3 non volatile memory: 48 byte user space environmental specifications operating temperature: 0c to +70c case power consumption: 6.0 w maximum
4 technical specifications absolute maximum ratings 1 recommended operating conditions 2 notes: 1. absolute maximum ratings are those values beyond which functional performance is not intended, device reliability is not impl ied, and damage to the device may occur. 2. typical operating conditions are those values for which functional performance and device reliability is implied. r e t e m a r a pm u m i n i ml a c i p y tm u m i x a ms t i n us e t o n e r u t a r e p m e t e g a r o t s0 5 8c e r u t a r e p m e t g n i t a r e p o0 0 7c e r u t a r e p m e t e s a c ) v 3 . 3 ( e g a t l o v y l p p u s 6 . 3v ) v 8 . 1 ( e g a t l o v y l p p u s 0 . 2v n i p i u a x y n a n o e g a t l o v 5 . 2v n i p s o m c v l y n a n o e g a t l o v7 . 0 -0 . 4v r e t e m a r a pm u m i n i ml a c i p y tm u m i x a ms t i n us n o i t i d n o c e m i t n o i t a z i l i b a t s5 . 05 c e s e g a t l o v t u p n i5 3 1 . 33 . 35 6 4 . 3v ) s p a ( e g a t l o v t u p n i1 7 . 18 . 19 8 . 1v ) v 3 . 3 @ ( t n e r r u c y l p p u s5 . 16 . 1a ) v 8 . 1 @ ( t n e r r u c y l p p u s5 1 . 04 . 0a n o i t p m u s n o c r e w o p2 . 50 . 6w g u l p t o h g n i r u d t n e r r u c h s u r n i 0 5s m / a m ) n i p r e w o p r e p ( t n e r r u c h s u r n i 5 7 . 0a e t a t s y d a e t s a 5 . 0 x % 0 5 1 g n i t a r
5 optical specifications r e t e m a r a pm u m i n i ml a c i p y tm u m i x a ms t i n us e t o n r e t t i m s n a r t r e w o p t u p t u o a m o r e s a l2 . 5 -a m o m b d2 , 1 r e w o p t u p t u o n a e m r e s a l2 . 8 -5 . 0n a e m m b d3 , 2 , 1 o i t a r n o i t c n i t x e5 . 3-b d2 , 1 h t g n e l e v a w0 6 2 15 5 3 1m n y t l a n e p n o i s r e p s i d d n a r e t t i m s n a r t ) p d t ( 2 . 3b d2 , 1 o i t a r n o i s s e r p p u s e d o m e d i s0 3b d1 p d t - a m o2 . 6 -a m o m b d2 , 1 n i r 2 1 a m o8 2 1 -z h / b d1 s s o l n r u t e r l a c i t p o2 1b d n o i t i n i f e d e y e x t 2 e r u g i f e e s r e v i e c e r y t i v i t i s n e s d e s s e r t s- 3 . 0 1 -a m o m b d1 y t i v i t i s n e s l a n i m o n- 6 . 2 1 -a m o m b d3 , 1 d a o l r e v o r e w o p e v i e c e r5 . 0n a e m m b d4 , 1 s s o l e c n a t c e l f e r 2 1 -b d1 h t g n e l e v a w0 6 2 15 5 3 1m n1 n o t c e t e d l a n g i s0 3 -m b d f f o t c e t e d l a n g i s 6 1 -m b d s i s e r e t s y h t c e t e d l a n g i s5 . 0b d general specification considerations (notes) 1. ieee 802.3ae compliant. 2. these parameters are interrelated: see ieee 802.3ae. 3. information purposes only. 4. up to 1.5db without damage. note: where x1, x2, x3, y1, y2, y3 = 0.25, 0.40, 0.45, 0.25, 0.28, 0.40 respectively figure 2. transmitter eye mask definition
6 electrical mdio parameters table 2 - mdio 1.2 v dc parameters table 3 - mdio ac parameters r e t e m a r a pn o i t p i r c s e dm u m i n i ml a c i p y tm u m i x a ms t i n us n o i t i d n o c h o ve g a t l o v h g i h t u p t u o0 . 15 . 1v a u 0 0 1 - = h o i l o ve g a t l o v w o l t u p t u o3 . 0 -2 . 0v a u 0 0 1 + = l o i l o it n e r r u c w o l t u p t u o4 -a m3 . 0 = n i v h i ve g a t l o v h g i h t u p n i4 8 . 05 . 1v l i ve g a t l o v w o l t u p n i3 . 0 -6 3 . 0v n i ce c n a t i c a p a c t u p n i0 1f p r e t e m a r a pn o i t p i r c s e dm u m i n i ml a c i p y tm u m i x a ms t i n us n o i t i d n o c d l o h te m i t d l o h a t a d o i d m0 1s n p u t e s te m i t p u t e s a t a d o i d m0 1s n y a l e d to t e g d e g n i s i r c d m m o r f y a l e d e g n a h c a t a d o i d m 00 0 3s n x a m fe t a r k c o l c c d m m u m i x a m5 . 2z h m electrical control and sense i/o parameters table 1 - cmos dc parameters (tx_fault, mdc, prtad<4:0>, lasi) ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 0 . 1t e s e rt e s e r d m p / a m p = 1 n o i t a r e p o l a m r o n = 0 w r 4 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 3 1 . 0 . 1n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r1 2 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 1 1 . 0 . 1r e w o p w o le d o m r e w o p w o l = 1 n o i t a r e p o l a m r o n = 0 w r0 7 : 0 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 6 . 0 . 1n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r1 2 : 5 . 0 . 1n o i t c e l e s d e e p s2 3 4 5 d e v r e s e r = x x x 1 d e v r e s e r = x x 1 x d e v r e s e r = x 1 x x d e v r e s e r = 1 0 0 0 s / b g 0 1 = 0 0 0 0 w r 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a s e u l a vw r 0 . 0 . 1k c a b p o o l a m pe d o m k c a b p o o l a m p e l b a n e = 1 e d o m k c a b p o o l a m p e l b a s i d = 0 w r0
7 electrical high speed i/o parameters table 4 - 3.125 gb/s xaui input interface r e t e m a r a pn o i t p i r c s e dm u m i n i ml a c i p y tm u m i x a ms t i n us n o i t i d n o c e t a r d u a b5 2 1 . 3s / b g e c n a r e l o t e t a r d u a b0 0 1 -0 0 1m p p e d u t i l p m a t u p n i l a i t n e r e f f i d0 0 20 0 5 2p p v m1 e t o n s s o l n r u t e r l a i t n e r e f f i d0 1 -b df e r z h g 5 . 2 o t z h m 0 0 1 0 0 1 o t w e c n a d e p m i s s o l n r u t e r e d o m n o m m o c6 -b df e r z h g 5 . 2 o t z h m 0 0 1 5 2 o t w w e k s l a i t n e r e f f i d t u p n i5 7p - p s p2 e t o n , t n i o p g n i s s o r c t a e c n a r e l o t e d u t i l p m a r e t t i j + r e t t i j m o d n a r + c i t s i n i m r e t e d r e t t i j j s j s + 5 5 . 0p p i uj s r o f a 2 e r u g i f e e s h p a r g r e t t i j r e t e m a r a pn o i t p i r c s e dm u m i n i ml a c i p y tm u m i x a ms t i n us n o i t i d n o c e t a r d u a b5 2 1 . 3s / b g n o i t a i r a v e t a r d u a b0 0 1 -0 0 1m p p e d u t i l p m a l a i t n e r e f f i d0 0 80 0 6 1p p v m ) % 0 8 - 0 2 ( s e m i t n o i t i s n a r t0 60 90 3 1s p2 e t o n r e t t i j t u p t u o l a t o t5 7 1 . 0 i un o i t a z i l a u q e - e r p o n r e t t i j c i t s i n i m r e t e d t u p t u o5 8 0 . 0 i un o i t a z i l a u q e - e r p o n w e k s l a i t n e r e f f i d t u p t u o5 1s pt n i o p g n i s s o r c t a s s o l n r u t e r t u p t u o l a i t n e r e f f i d b d5 2 6 o t z h m 5 . 2 1 3 b d 0 1 - : z h m : z h g 5 2 1 . 3 o t z h m 5 2 6 1 - 7 4 n o i t a u q e r e p s a e a 3 . 2 0 8 e e e i k s a m e y e l a c i r t c e l e 3 e r u g i f e e s figure 2a. single-tone sinusoidal jitter mask table 5 - 3.125 gb/s xaui driver characteristics note: 1. maximum amplitude of 2500 mvpp is the combined effect of the driver maximum output signal of 1600 mvpp and the receiver input impedance mismatch. 2. for information only.
8 electrical eye mask figure 3 - xaui driver near end template 800 400 0 -400 -800 differential amplitude (mv) 0 x1 = 0.175 1-x1 = 0.825 1 x2 = 0.390 1-x2 = 0.610 time in ui general connector considerations 1. ground connections are common for tx and rx. 2. v cc contacts are each rated at 0.5 a nominal. 3. see figure 8 for layout of host pcb and location of pin1.
9 table 6 - general i/o pin summary e p y t l a n g i ss n i pn o i t c e r i dn o i t c n u f n i p y l p p u s r e w o p s d n u o r g, 7 5 , 4 5 : 2 5 , 9 4 , 6 4 , 3 4 , 0 4 , 7 3 : 3 3 , 3 : 1 0 7 : 9 6 , 6 6 , 3 6 , 0 6 d n u o r g l a c i r t c e l e v 3 . 31 3 : 0 3 , 6 : 5i y l p p u s r e w o p v 3 . 3 v 0 . 52 3 , 4i d e s u t o n y l p p u s r e w o p v 0 . 5 y l p p u s r e w o p e v i t p a d a9 2 : 8 2 , 8 : 7i ) v 8 . 1 ( y l p p u s r e w o p e v i t p a d a t e s y l p p u s r e w o p e v i t p a d a5 2i n o i t c e n n c c t e s s p a e s n e s y l p p u s r e w o p e v i t p a d a7 2i n o i t c e n n o c e s n e s s p a s n i p o / i e s n e s & l o r t n o c i s a l9o t s o h n o p u l l u p s o m c v 2 . 1 t e s e r0 1i e l u d o m n o p u l l u p s o m c v 2 . 1 f f o / n o r e t t i m s n a r t2 1i e l u d o m n o p u l l u p s o m c v 2 . 1 0 : 4 s s e r d d a t r o p3 2 : 9 1i e l u d o m n o p u l l u p s o m c v 2 . 1 s n i p o i d m t c e t e d d o m4 1o n o d n u o r g o t n w o d l l u p w k 1 e l u d o m o i a t a d t n e m e g a n a m7 1o / i3 . 5 4 e s u a l c e a 3 . 2 0 8 e e e i r e p v 2 . 1 k c o l c a t a d t n e m e g a n a m8 1i 3 . 5 4 e s u a l c e a 3 . 2 0 8 e e e i r e p v 2 . 1 s n i p o / i d e e p s h g i h + 3 : 0 e n a l r e v i e c e r0 5 , 7 4 , 4 4 , 1 4o 7 4 e s u a l c e a 3 . 2 0 8 e e e i r e p i u a x - 3 : 0 e n a l r e v i e c e r1 5 , 8 4 , 5 4 , 2 4o 7 4 e s u a l c e a 3 . 2 0 8 e e e i r e p i u a x + 3 : 0 e n a l r e t t i m s n a r t4 6 , 1 6 , 8 5 , 5 5i 7 4 e s u a l c e a 3 . 2 0 8 e e e i r e p i u a x - 3 : 0 e n a l r e t t i m s n a r t5 6 , 2 6 , 9 5 , 6 5i 7 4 e s u a l c e a 3 . 2 0 8 e e e i r e p i u a x s n i p d e t c e n n o c n o n d e t c e n n o c t o n, 9 3 : 8 3 , 2 3 , 6 2 , 4 2 , 6 1 : 5 1 , 3 1 , 1 1 , 4 8 6 : 7 6 e l u d o m n o c n
10 electrical pin out 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 prtad2 prtad1 prtad0 not connected aps set not connected aps sense aps aps 3.3v 3.3v 5.0v gnd gnd gnd gnd 5.0v 3.3v 3.3v aps aps lasi reset not connected tx on/off not connected mod detect not connected not connected mdio mdc prtad4 prtad3 gnd gnd 1 2 3 4 5 6 7 8 9 gnd gnd gnd gnd gnd 70 69 53 52 51 49 48 47 46 45 44 43 42 40 39 38 37 36 50 41 not connected not connected gnd tx lane3- tx lane3+ gnd tx lane2- tx lane2+ gnd tx lane1- tx lane1+ gnd tx lane0- tx lane0+ 68 67 66 65 64 63 62 61 59 58 57 56 55 60 gnd 54 gnd rx lane2- rx lane2+ gnd rx lane1- rx lane1+ gnd rx lane0- rx lane0+ gnd not connected not connected rx lane3- rx lane3+ gnd figure 4. electrical pin out
11 electrical pin out definitions table 7 - pin function definitions (lower row) o n n i pe m a nn o i t c e r i dn o i t c n u fe t o n 1d n gd n u o r g l a c i r t c e l e 2d n gd n u o r g l a c i r t c e l e 3d n gd n u o r g l a c i r t c e l e 4d e t c e n n o c t o ny l p p u s r e w o p v 0 . 5 5v 3 . 3i y l p p u s r e w o p v 3 . 3 6v 3 . 3i y l p p u s r e w o p v 3 . 3 7s p ai ) v 8 . 1 ( y l p p u s r e w o p e v i t p a d a 8s p ai ) v 8 . 1 ( y l p p u s r e w o p e v i t p a d a 9i s a lo n o i t a r e p o l a m r o n : h g i h c i g o l d e t r e s s a i s a l : w o l c i g o l 0 1 e l b a t e e s 0 1t e s e ri o i t a r e p o l a m r o n : h g i h c i g o l t e s e r : w o l c i g o l 1 1d e t c e n n o c t o n 2 1f f o / n o x ti k 0 1 a i v e l u d o m e d i s n i p u d e l l u p w n o r e t t i m s n a r t : h g i h c i g o l f f o r e t t i m s n a r t : w o l c i g o l 3 1d e t c e n n o c t o n 4 1t c e t e d d o mo d n g o t k 1 h g u o r h t e l u d o m e d i s n i w o l d e l l u p 5 1d e t c e n n o c t o n 6 1d e t c e n n o c t o n 7 1o i d mo / io i a t a d t n e m e g a n a m 8 1c d mi k c o l c a t a d t n e m e g a n a m 9 14 d a t r pi 4 t i b s s e r d d a t r o p 0 23 d a t r pi 3 t i b s s e r d d a t r o p 1 22 d a t r pi 2 t i b s s e r d d a t r o p 2 21 d a t r pi 1 t i b s s e r d d a t r o p 3 20 d a t r pi 0 t i b s s e r d d a t r o p 4 2d e t c e n n o c t o n 5 2t e s s p ai n o i t c e n n o c t e s s p a 6 2d e t c e n n o c t o n 7 2e s n e s s p ai n o i t c e n n o c e s n e s s p a 8 2s p ai ) v 8 . 1 ( y l p p u s r e w o p e v i t p a d a 9 2s p ai ) v 8 . 1 ( y l p p u s r e w o p e v i t p a d a 0 3v 3 . 3ir e w o p 1 3v 3 . 3ir e w o p 2 3d e t c e n n o c t o ny l p p u s r e w o p v 0 . 5 3 3d n gd n u o r g l a c i r t c e l e 4 3d n gd n u o r g l a c i r t c e l e 5 3d n gd n u o r g l a c i r t c e l e
12 table 8 - pin function definitions (upper row) o n n i pe m a nn o i t c e r i dn o i t c n u fe t o n 6 3d n gd n u o r g l a c i r t c e l e 7 3d n gd n u o r g l a c i r t c e l e 8 3d e t c e n n o c t o n 9 3d e t c e n n o c t o n 0 4d n gd n u o r g l a c i r t c e l e 1 4+ 0 e n a l x ro + 0 e n a l t u p t u o i u a x e l u d o m 2 4- 0 e n a l x ro - 0 e n a l t u p t u o i u a x e l u d o m 3 4d n gd n u o r g l a c i r t c e l e 4 4+ 1 e n a l x ro + 1 e n a l t u p t u o i u a x e l u d o m 5 4- 1 e n a l x ro - 1 e n a l t u p t u o i u a x e l u d o m 6 4d n gd n u o r g l a c i r t c e l e 7 4+ 2 e n a l x ro + 2 e n a l t u p t u o i u a x e l u d o m 8 4- 2 e n a l x ro - 2 e n a l t u p t u o i u a x e l u d o m 9 4d n gd n u o r g l a c i r t c e l e 0 5+ 3 e n a l x ro + 3 e n a l t u p t u o i u a x e l u d o m 1 5- 3 e n a l x ro - 3 e n a l t u p t u o i u a x e l u d o m 2 5d n gd n u o r g l a c i r t c e l e 3 5d n gd n u o r g l a c i r t c e l e 4 5d n gd n u o r g l a c i r t c e l e 5 5+ 0 e n a l x ti + 0 e n a l t u p n i i u a x e l u d o m 6 5- 0 e n a l x ti - 0 e n a l t u p n i i u a x e l u d o m 7 5d n gd n u o r g l a c i r t c e l e 8 5+ 1 e n a l x ti + 1 e n a l t u p n i i u a x e l u d o m 9 5- 1 e n a l x ti - 1 e n a l t u p n i i u a x e l u d o m 0 6d n gd n u o r g l a c i r t c e l e 1 6+ 2 e n a l x ti + 2 e n a l t u p n i i u a x e l u d o m 2 6- 2 e n a l x ti - 2 e n a l t u p n i i u a x e l u d o m 3 6d n gd n u o r g l a c i r t c e l e 4 6+ 3 e n a l x ti + 3 e n a l t u p n i i u a x e l u d o m 5 6- 3 e n a l x ti - 3 e n a l t u p n i i u a x e l u d o m 6 6d n gd n u o r g l a c i r t c e l e 7 6d e t c e n n o c t o n 8 6d e t c e n n o c t o n 9 6d n gd n u o r g l a c i r t c e l e 0 7d n gd n u o r g l a c i r t c e l e
13 mechanical specifications package dimensions figure 5. note: it is recommended that the user refers to the xenpak msa at www.xenpak.org for full mechanical detail.
14 dimensions table (figure 5) y e ks e u l a ve c n a r e l o ts t n e m m o c m mh c n im m 1 a3 . 1 50 2 0 . 20 2 . 0 l l a r e v o l e z e b f o h t d i w 1 b4 . 2 22 8 8 . 00 2 . 0 l l a r e v o l e z e b f o t h g i e h 1 e5 7 . 0 27 1 8 . 0m u m i x a mw e r c s e v i t p a c f o n o i s n e t x e 1 f0 . 6 37 1 4 . 10 2 . 0 y d o b r e v i e c s n a r t f o h t d i w 1 k) 0 . 1 2 1 (4 6 7 . 4f e r s d a e h w e r c s e v i t p a c g n i d u r t o r p s u n i m l l a r e v o r e v i e c s n a r t f o h t g n e l 1 l0 0 . 57 9 1 . 00 2 . 0 d n e d e d a e r h t f o d n e o t " d " m u t a d m o r f w e r c s e v i t p a c f o h t g n e l 1 n8 . 58 2 2 . 00 2 . 0 l e z e b r e v i e c s n a r t f o t n o r f o t " d " m u t a d 1 v2 9 . 72 1 3 . 00 2 . 0 l e z e b r e v i e c s n a r t f o m o t t o b o t " e " m u t a d 1 y0 2 . 2 0 14 2 0 . 40 2 . 0 " b " m u t a d o t " d " m u t a d 1 a a0 . 38 1 1 . 00 5 . 0 r e f m a h c 5 4 f o d n e o t " b " m u t a d 1 b b) 2 . 5 1 1 (5 3 5 . 4f e r e g d e l g n i g n a h - r e v o r a e r o t " d " m u t a d m o r f e l u d o m f o h t g n e l 1 l l8 . 5 26 1 0 . 1m u m i x a mw e r c s b m u h t f o h t g n e l
15 figure 6.
16 note: case ground is separated from the common rx and tx signal ground figure 7.
17 pin1 figure 8. host board layout for 70 pin connector
18 functional descriptions block diagram figure 9 shows a block diagram of the HFCT-701XBD. figures 10 and 11 show greater detail of the transmitter and receiver paths. electrical connector system control HFCT-701XBD other signals 8b/10b 3.125 x 4 serdes 64b/66b 10g serdes mdio opto opto optical connectors figure 9. block diagram of HFCT-701XBD figure 10. transmit path high level overview transmitter path summary figure 10 shows a block diagram of the transmit path, from the four xaui differential inputs to the optical output. the incoming 4 x 3.125 gb/s xaui differential 8b/10b encoded electrical inputs, are reformatted and transmitted onto the outgoing fiber optic interface at 10.3125 gb/s, using 64b/66b encoding. sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 64b/66b 1:0 block sync tx opto pll tx xtal mux 8b/10b decoder 64b/66b encoder rate adjust by add drop off |r| character cdr
19 receiver path summary figure 11 shows a block diagram of the receiver path, from the incoming 10.3125 gb/ s, 64b/66b encoded optical interface to the four 3.125 gb/ s differental 8b/10b encoded xaui electrical output interface. the xaui output drivers provide low-swing differential output with 100 w differential output impedance and are ac coupled. management data input/output (mdio) interface the mdio interface provides a simple, two wire, serial interface to connect a station management entity (sta) and a managed phy for the purpose of controlling the phy and gathering status from the phy. the management interface consists of the two wire physical interface, a frame format, a protocol specification for exchanging the frames and a register set that can be read and written using these frames. the two wires of the physical interface are the management data clock (mdc) and the management data i/o (mdio). figure 11. receive path high level overview management data clock (mdc) the mdc is sourced by the station management entity (sta) to the phy as the timing reference for transfer of information on the mdio signal. mdc is an aperiodic signal that has no maximum high or low times. management data i/o (mdio) mdio is a bidirectional signal between the phy (hfct- 701xbd) and the sta. it is used to transfer control and status information. data is always driven and sampled synchronously with respect to mdc. figure 13 shows the mdio open drain driver configuration. mdio timing relationship to mdc mdio is a bidirectional signal that can be sourced by the sta or the HFCT-701XBD. when the sta sources the mdio signal, the sta shall provide a minimum of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge of mdc (see figure 12). when the mdio signal is sourced by the hfct- 701xbd, it is sampled by the sta synchronously with respect to the rising edge of mdc. the clock output delay from the HFCT-701XBD shall be a minimum of 0 ns and a maximum of 300 ns. mdc mdio (sta sourced) tsu=10 ns min data valid thd=10 ns min mdc mdio (HFCT-701XBD sourced) data valid tpd=0 ns min, 300 ns max figure 12. mdio/mdc timing pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 driver rx opto de mux xtal 8b/10b encoder 64b/66b decoder rate adjust mux cdr clock for rx 10g path
20 open drain driver coregnd mdio pin 1.2 v pullup, r>100 ohms external capacitance loading c< 700 pf receive buffer figure 13. mdio open drain driver configuration table 9. frame format management frame format the HFCT-701XBD has an internal address register which is used to store the address for mdio reads and writes. this mdio address register can be set by using an address frame that specifies the register address to be accessed within a particular port device. the following write, read or a post-read-increment-address frame to the same port device shall access the register whose address is stored in the hfct- 701xbd mdio address register. an address frame should be followed immediately by its associated write, read or post- read-increment-address frame. upon receiving a post-read- increment-address frame and having completed the read operation, the HFCT-701XBD shall increment and store the address of the register accessed. if no address cycle is received before the next write, read or post-read-increment- address frame, then the hfct- 701xbd shall use the stored address for that register access. the management frame format for indirect access is specified in table 9. pre - preamble at the beginning of each transaction the sta shall send a preamble sequence of 32 contiguous logic one bits on mdio with 32 corresponding cycles on mdc, to provide the HFCT-701XBD with a pattern that it can use to establish synchronization. the hfct- 701xbd must observe this preamble sequence before it responds to any transaction. st - start the start of frame is indicated by a <00> pattern. this pattern ensures transitions from the default logic one line to zero and back to one. s d l e i f e m a r f t n e m e g a n a m e m a r fe r pt sp od a t r pd a v e da ta t a d / r d d ae l d i s s e r d d a1 . . . 10 00 0] 0 : 4 [ d a t r p] 0 : 4 [ a d0 1] 0 : 5 1 [ dz e t i r w1 . . . 10 01 0] 0 : 4 [ d a t r p] 0 : 4 [ a d0 1] 0 : 5 1 [ dz d a e r1 . . . 10 01 1] 0 : 4 [ d a t r p] 0 : 4 [ a d0 z] 0 : 5 1 [ dz c n i d a e r1 . . . 10 00 1] 0 : 4 [ d a t r p] 0 : 4 [ a d0 z] 0 : 5 1 [ dz op - operation code table 10. op code definitions prtad the port address is five bits, allowing 32 unique port addresses. HFCT-701XBDs port address is set through pins prtad<0:4>. devad the device address is five bits, allowing 32 unique devices per port. the HFCT-701XBD supports device addresses 1 (pma/pmd), 3 (pcs) and 4 (phy xs). ta the turnaround time is a two bit time spacing between the register address field and the data field of a management frame to avoid contention during a read transaction (see ieee 802.3ae). e d o c p on o i t a r e p o 0 0s s e r d d a r e t s i g e r 1 0a t a d e t i r w 1 1a t a d d a e r 0 1t n e m e r c n i + a t a d d a e r t s o p addr/data the data/address field is 16 bits. the first bit transmitted/ received is bit 15 and the last bit is bit 0. idle the idle condition is a high- impedance state. the mdio line will be pulled to a one. eeprom interface nvr there are two main memory/ register types in the hfct- 701xbd which comply with the ieee 802.3ae and xenpak standard: volatile and nonvolatile. these areas can be further divided into user readable and writeable areas. at power up the module register space is initialized and, where appropriate, default values are loaded from the non user accessible nonvolatile memory. the user accessible nonvolatile memory is also uploaded entirely into the user accessible volatile memory.
21 figure 14. mdio frame formats mdc mdio write 32 "1"s 0000 a4 a3 a0 r4 r3 r0 0 1 a15 a14 a1 a0 idle preamble st op code phy address register address turn around address idle write device management interface - address frame structure mdc mdio write 32 "1"s 0001 a4 a3 a0 r4 r3 r0 0 1 d15 d14 d1 d0 idle preamble st op code phy address register address turn around data idle write device management interface - write frame structure mdc mdio read increment 32 "1"s 0010 a4 a3 a0 r4 r3 r0 0 z d15 d14 d1 d0 idle preamble st op code phy address register address turn around data idle write device management interface - read increment frame structure read mdc mdio read 32 "1"s 0011 a4 a3 a0 r4 r3 r0 0 z d15 d14 d1 d0 idle preamble st op code phy address register address turn around data idle write device management interface - read frame structure read
22 it is important to note that writes to the user accessible volatile memory are not stored to the corresponding user nonvolatile area and will therefore be lost upon a power down or reset. for such writes to be permanent the data must be written first to the user accessible nonvolatile area and then a reload invoked via the nvr control/status register, see register 1.32768. access the xenpak msa related nonvolatile control/status register is only needed for performing writes to the nonvolatile user accessible area within the HFCT-701XBD because nonvolatile memory cannot be written to by normal mdio write cycles. other writes to volatile memory and registers may be performed directly via normal mdio write cycles. all volatile and nonvolatile locations may be read directly via mdio read cycles, it is not necessary to use the nvr control/status register, other than for status. read/write command (bit5) the xenpak msa related 1.32768.5 register must be set to 1 to perform writes to the nvr and zero (read) otherwise a zero written to bit 5 initiates an nvr read. a 1 written to bit 5 initiates an nvr write. if the nvr register bit 5 is set to zero and the extended command bits set to 11 forces an upload of all values in the nvr to the volatile areas, including default register values. such an upload is performed automatically after a hard or soft reset. eeprom checksum checking the HFCT-701XBD will perform a checksum calculation and compare after every successful 256 byte read. the checksum for comparison is in eeprom register 118 =mdio register 1.32893.7:0. the checksum is equal to the 8 lsb s of the sum of bytes 0 to 117 of the eeprom. the calculated checksum is stored in mdio register 1.49156.15:8. the result of the calculated checksum compared with the one read from eeprom is placed in mdio register 1.49155.7. eeprom 256 byte read cycle an eeprom 256 byte read cycle is initiated by setting mdio bits 1.32768.0,1 to 0 and 1.32768.5 to 0. the information to be read from the eeprom stored in the 256 mdio registers. a 256 byte read is initiated on hot- plug or reset. eeprom single byte read or write cycle an eeprom single byte read/ write cycle is initiated by setting mdio eeprom control register bits 1.32768.1:0 to 10. as for the 256 byte read/write commands, mdio register 1.32768.5 determines if a read or a write cycle will be performed. the single byte eeprom address is read from eeprom control register 1.32768 bit15:8. the data is placed in/read from the associated mdio register. monitors and diagnostic features the lasi pin is used to indicate suboptimal performance in either the receive or transmit path. it can be used as an interrupt. it is the or of the tx_alarm, rx_alarm and the ls_alarm signals each gated with their respective enables. the enables are read from mdio register 1.36867, lasi control. lasi ={or of (reg 1.36869.n bit wise and reg 1.36866.n) for n=0 to 15}. n o i t p i r c s e ds r e t s i g e r s u t a t s o i d me p y ts r e t s i g e r e l b a n e o i d me u l a v t l u a f e d m r a l a _ s l0 . 9 6 8 6 3 . 1h l / o r0 . 6 6 8 6 3 . 10 m r a l a _ x t1 . 9 6 8 6 3 . 1h l / o r1 . 6 6 8 6 3 . 10 m r a l a _ x r2 . 9 6 8 6 3 . 1h l / o r2 . 6 6 8 6 3 . 10 e d o m t s e t i s a l3 . 9 6 8 6 3 . 1w r3 . 6 6 8 6 3 . 10 w o l o o t y l p p u s v 8 . 14 . 9 6 8 6 3 . 1h l / o r4 . 6 6 8 6 3 . 10 w o l o o t y l p p u s v 3 . 35 . 9 6 8 6 3 . 1h l / o r5 . 6 6 8 6 3 . 10 w o l o o t e g a t l o v n i _ v 3 p 3 n o m6 . 9 6 8 6 3 . 1h l / o r6 . 6 6 8 6 3 . 10 table 11. lasi control registers
23 ls_alarm ls alarm is latched high each time the link_status signal changes state. ls_alarm is the output of this latch and the ls_alarm enable register (see figure 15). link_status is an indicator of the link health. link_status = {pmd signal detect (mdio 1.10.0) and pcs block_lock (mdio 3.32.0) and n o i t p i r c s e ds u t a t s o i d m ) o r ( s r e t s i g e r s r o r r i me p y te l b a n e o i d m ) w / r ( s r e t s i g e r t l u a f e d t l u a f l a c o l e v i e c e r s x _ y h p0 . 7 6 8 6 3 . 10 1 . 8 . 4h l / o r0 . 4 6 8 6 3 . 11 r o r r e e t a r e v i e c e r s x _ y h p1 . 7 6 8 6 3 . 13 . 4 5 1 9 4 . 1h l / o r1 . 4 6 8 6 3 . 10 n o i t a l o i v e d o c e v i e c e r s c p2 . 7 6 8 6 3 . 1h l / o r2 . 4 6 8 6 3 . 10 t l u a f l a c o l e v i e c e r s c p3 . 7 6 8 6 3 . 11 1 . 8 . 3h l / o r3 . 4 6 8 6 3 . 10 t l u a f l a c o l e v i e c e r a m p4 . 7 6 8 6 3 . 11 1 . 8 . 1h l / o r4 . 4 6 8 6 3 . 11 r o r r e r e w o p e v i e c e r5 . 7 6 8 6 3 . 1h l / o r5 . 4 6 8 6 3 . 10 table 12. receive alarm registers figure 15. tx lasi signals phy_xs lane_alignment (mdio 4.24.12)} rx_alarm rx_alarm is used to indicate a problem with the receive path. rx_alarm is the or of several receive path status registers in mdio registers 1.36867. the oring of each term is enabled by a companion mdio register 1 * phy xgxs tx local 4.8.11 = 1 (en 1.36865.0=1) 2 * phy xgxs tx code 1.36868.1 = (en 1.36865.1=1) 3 * phy xgxs tx rate 1.49154.5 = (en 1.36865.2=1) 4 * pcs local tx 3.8.11 = 1 (en 1.36865.3=1) 5 * pma local tx 1.8.11 = 1 (en 1.36865.4=1) 6 * tx pll latched loss of 1.36868.5 = (en 1.36865.5=1) 7 * latched version of tx 1.36868.6 = (en 1.36865.6=1) sipo and code alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 status 4 xaui lane 0 status 1,2 status 1,3 64b/66b 1:0 block sync tx opto pll tx xtal tx pll ok 1.49153.0 status 4 status 5 status 6 mux 8b/10b decoder 64b/66b encoder rate adjust by add drop off |r| character cdr in 1.36864 and the overall output is enabled by the rx_alarm enable register (1.36866.2). rx_alarm ={or of (reg 1.36867 bit wise and reg 1.36864..n) for n=0 to 15} and {rx_alarm enable (1.36866.2})
24 table 13. transmit alarm registers tx_alarm tx_alarm is used to indicate a problem with the transmit path. tx_alarm is the or of several transmit path status registers in mdio registers n o i t p i r c s e ds u t a t s o i d m ) o r ( s r e t s i g e r s r o r r i me p y te l b a n e o i d m ) w / r ( s r e t s i g e r t l u a f e d t l u a f l a c o l t i m s n a r t s x _ y h p0 . 8 6 8 6 3 . 11 1 . 8 . 4h l / o r0 . 5 6 8 6 3 . 11 r o r r e e d o c s x _ y h p1 . 8 6 8 6 3 . 1- h l / o r1 . 5 6 8 6 3 . 10 r o r r e e t a r t i m s n a r t s x _ y h p2 . 8 6 8 6 3 . 15 . 4 5 1 9 4 . 1h l / o r2 . 5 6 8 6 3 . 10 t l u a f l a c o l t i m s n a r t s c p3 . 8 6 8 6 3 . 11 1 . 8 . 3h l / o r3 . 5 6 8 6 3 . 11 t l u a f l a c o l t i m s n a r t a m p4 . 8 6 8 6 3 . 11 1 . 8 . 1h l / o r4 . 5 6 8 6 3 . 11 k c o l x t f o n o i s r e v d e h c t a l5 . 8 6 8 6 3 . 10 . 3 5 1 9 4 . 1h l / o r5 . 5 6 8 6 3 . 10 t l u a f x t f o n o i s r e v d e h c t a l6 . 8 6 8 6 3 . 1h l / o r6 . 5 6 8 6 3 . 11 t l u a f r e w o p t u p t u o x t7 . 8 6 8 6 3 . 1h l / o r7 . 5 6 8 6 3 . 10 t l u a f e r u t a r e p m e t r e s a l8 . 8 6 8 6 3 . 1h l / o r8 . 5 6 8 6 3 . 10 t l u a f t n e r r u c s a i b r e s a l9 . 8 6 8 6 3 . 1h l / o r9 . 5 6 8 6 3 . 10 1.36868 bit wise andd with the tx_alarm enable register. the oring of each term is enabled by a companion mdio register in 1.36865. tx_alarm = {or of (reg 1.36868 bit wise and reg 1.36865) for n=0 to 15} and {tx_alarm enable (reg 1.36866.1)} 1 * phy xgxs tx local fault 4.8.11 = 1 and (en 1.36865.0=1) 2 * phy xgxs tx code error 1.36868.1 = 1 and (en 1.36865.1=1) 3 * phy xgxs tx rate error 1.49154.5 = 1 and (en 1.36865.2=1) 4 * pcs local tx fault 3.8.11 = 1 and (en 1.36865.3=1) 5 * pma local tx fault 1.8.11 = 1 and (en 1.36865.4=1) 6 * tx pll latched loss of lock 1.36868.5 = 1 and (en 1.36865.5=1) 7 * latched version fo tx fault 1.36868.6 = 1 and (en 1.36865.6=1) 1 * phy xgxs rx local fault 4.8.10 = 1 and (en 1.36864.0=1) 2 * phy xgxs rx rate error 4.49154 = 1 and (en 1.36864.1=1) 3 * 64b/66b rx code violation 1.36867 = 1 and (en 1.36864.2=1) 4 * pcs local rx fault 3.8.11 = 1 and (en 1.36864.3=1) 5 * pma/d rx fault 1.8.10 and (en 1.36864.4=1) 6 * rx power error 1.49155.5 and (en 1.36864.5=1) 1 * pmd signal detect 1.10.0 (en 1.36864.0=1) 1 * pcs block_lock 3.32.0 (en 1.36864.0=1) 1 * phy_xs lane alignment 4.24.12 (en 1.36864h.0=1) ls_alarm 1.36869.0 (en 1.36866.0 0) tx_alarm 1.36869.1 (en 1.36866.1 0) rx_alarm 1.36869.2 (en 1.36866.2 0) lasi test mode 1.36869.3 (en 1.36866.3 0) 1.8v supply too low 1.36869.4 (en 1.36866.4 0) 3.3v supply too low 1.36867.5 (en 1.36866.5 0) latch link_status latch high on change of level reset low ls_alarm ls_alarm_enable tx_alarm tx_alarm_enable rx_alarm rx_alarm_enable lasi asserted on leading edge of read figure 16. lasi functional diagram
25 loopbacks when in any system (pma, pcs or xgxs system) loopback mode the HFCT-701XBD shall accept data from the transmit path and return it on the receive path. during pma loopback the xenpak module will transmit the data received at the xaui i/ps. in xgxs system loopback, the laser will default to mean power but without any modulation. in pcs loopback mode a continuous pattern of 0x0f0f will be output. transmit data will be output instead if the associated loopback data out enable bit is set high for the enabled loopback mode. e m a n k c a b p o o lk c a b p o o l n o i t c e r i d k c a b p o o l l o r t n o c r e t s i g e r h t a p d e s s a p y b t u p t u o t l u a f e d e l b a n e t u p t u o a t a d r e t s i g e r h t a p d e s s a p y b 1 = ' l o r t n o c t u p t u o k c a b p o o l m e t s y s a m p ] 1 [ x r > - x t0 . 0 . 1a t a d t i m s n a r ta na n k c a b p o o l s c px r > - x t4 1 . 0 . 3f 0 f 05 . 2 5 1 9 4 . 3a t a d t i m s n a r t k c a b p o o l k r o w t e n s x g x ) d r a d n a t s e a 3 . 2 0 8 ( x t > - x r4 1 . 0 . 4x r t a a t a d e v i e c e r i u a x a na n k c a b p o o l m e t s y s s x g x4 x r > - x t4 1 . 2 5 1 9 4 . 4o n , r e w o p n a e m n o i t a l u d o m 5 1 . 2 5 1 9 4 . 4a t a d t i m s n a r t k c a b p o o l k r o w t e n a m p1 x t > - x r4 . 3 5 1 9 4 . 1a t a d d e v i e c e r9 . 3 5 1 9 4 . 1i u a x x r t a e l d i table 14. loopback summary reset operation writing a 1 to any of mdio registers 1.0.15, 3.0.15 or 4.0.15 causes all the HFCT-701XBD registers to be reset to their default values. these bits are all self-clearing after the reset function is complete. pulling the reset pin low causes a full chip reset. writes to any bits of the control register while the reset is asserted are ignored. all status and control registers are reset to their default states. the nvr read sequence is started when reset goes high. mdio register bits 1.0.15, 3.0.15, and 4.0.15 will be held to 1 until the reset sequence is complete. when in pma network loopback mode, the recovered and retimed 10.3125 gbd signal is looped to the transmitter. the receive path xaui output data will be received data. xaui idle codes will be output instead of the received data if the network loopback data out enable bit is set high. in ieee 802.3ae standard xgxs network loopback the recovered received data is looped back to the transmit path in the xaui block. enabling of more than one loopback path is invalid. notes 1. pma system loopback requires a valid optical signal to be present on the rx to operate. however, if no valid optical signal exist, set bit 1.49153.10=1, then set 1.0 bit 0=1.
26 figure 17. HFCT-701XBD loopback modes phy xs network loopback lane 0 pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 enable network loopback 4.0.14=1 xaui lane 0 driver enable system loopback 4.49152.15=1 rx opto de mux xtal 8b/10b encoder 64b/66b decoder rate adjust mux cdr enable system loopback 4.49152.14=1 sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 cdr 64b/66b 1:0 block sync tx opto pll tx xtal force 1's on phy_xs loopback 4.49152.15=0 pma network loopback 1.49153.4=1 system loopback 1.0.0=1 mux 8b/10b decoder 64b/66b encoder phy xgxs system loopback lane 0 pcs system loopback xgxs system loopback 4.49152.14 xgxs network loopback 4.0.14=1 rate adjust by add drop off |r| character pma network loopback pma system loopback
27 internal clock functionality figure 18. transmit path figure 19. receive path sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 64b/66b 1:0 block sync tx opto pll tx xtal mux 8b/10b decoder 64b/66b encoder rate adjust by add drop off |r| character tx xaui clock domain recovered from incoming xaui link tx 10g clock domain derrived internally from precision oscillator cdr rx xaui clock domain derived internally from precision oscillator rx 10g clock domain recovered from incoming 10g link pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 xaui lane 0 driver rx opto de mux xtal 8b/10b encoder 64b/66b decoder rate adjust mux cdr clock for rx 10g path
28 HFCT-701XBD registers figure 20. summary of key receiver path registers figure 21. summary of key transmit path registers pll descrambler 1+x 39 +x 58 frame recovery (block sync) xaui lane 1 xaui lane 2 xaui lane 3 reset all x.15 = 1 xaui lane 0 driver bypass scrambler 3.49152.1 =1 reset pcs 3.49152.4=1 pma locked 1.1.2=1 rx opto de mux signal detect 1.10.0=1 rx clk rate error 1.49153.1 =1 1 * phy xgxs rx local fault 4.8.10 = 1 (en 1.36864.0=1) 2 * phy xgxs rx rate error 4.49154.6:9 = 1 (en 1.36864.1=1) 3 * 64b/66b rx code violation 1.36867.2 = 1 (en 1.36864.2=1) 4 * pcs local rx fault 3.8.10 = 1 (en 1.36864.3=1) 5 * pma/d rx fault 1.8.10 (en 1.36864.4=1) 6 * rx power error 1.36867.5 (en 1.36864.5=1) pll ok 4.49152.3 xtal reset tx xgxs 4.49152.0=1 in service pcs bit error counter 3.33.13:8 in service errored block counter 3.33.7:0 status 1,2 status 1 status 3,4 from de-scrambler frame recovery cdr status 4 status 5 8b/10b encoder 64b/66b decoder rate adjust mux cdr status 6 clock for rx 10g path lock 4.49152.7:4 sync 4.24.3:0 lanes aligned 4.24.12=1 pll ok 4.49152.3 phy xgxs link up 4.1.2 = 1 bypass 3.49152.2 =1 reset pcs 3.49152.3=0 transmit disable 1.9.0 1 * phy xgxs tx local fault 4.8.11 = 1 (en 1.36865.0=1) 2 * phy xgxs tx code error 1.36868.1 = 1 (en 1.36865.1=1) 3 * phy xgxs tx rate error 1.36868.2 = 1 (en 1.36865.2=1) 4 * pcs local tx fault 3.8.11 = 1 (en 1.36865.3=1) 5 * pma local tx fault 1.8.11 = 1 (en 1.36865.4=1) 6 * tx pll latched loss of lock 1.36868.5 = 1 (en 1.36865.5=1) 7 * latched version fo tx fault 1.36868.6 = 1 (en 1.36865.6=1) sipo and code word alignment, with |k| char lane alignment, with |a| character. pll scrambler 1+x 39 +x 58 rate adjust & frame xaui lane 1 xaui lane 2 xaui lane 3 status 4 xaui lane 0 legend * = lasi signal status 1,2 status 1,3 64b/66b 1:0 block sync from rx 64b/66b encoder error 3.49152.0 = 1 tx opto pll tx xtal tx pll ok 1.49153.0 status 4 status 5 status 6 mux 8b/10b decoder 64b/66b encoder rate adjust by add drop off |r| character reset all x.15 = 1 cdr
29 HFCT-701XBD device 1 pma/pmd registers e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e r 10 0 1 l o r t n o c d m p / a m p 11 1 1 s u t a t s d m p / a m p 12 2 3 3 r e i f i t n e d i e c i v e d 14 4 y t i l i b a d e e p s d m p / a m p 15 5 6 6 e g a k c a p n i s e c i v e d 17 7 2 l o r t n o c d m p / a m p g 0 1 18 8 2 s u t a t s d m p / a m p g 0 1 19 9 e l b a s i d t i m s n a r t d m p g 0 1 10 1a t c e t e d l a n g i s e v i e c e r d m p g 0 1 14 1e 5 1f ) i u o ( r e i f i t n e d i e g a k c a p 18 6 7 2 30 0 0 8s u t a t s / l o r t n o c r v n 15 7 7 2 37 0 0 8d e t r o p p u s n o i s r e v a s m k a p n e x 16 7 7 2 38 0 0 87 7 7 2 39 0 0 8s e t y b n i e z i s r v n 18 7 7 2 3a 0 0 89 7 7 2 3b 0 0 8d e s u s e t y b f o r e b m u n 10 8 7 2 3c 0 0 8s s e r d d a d l e i f c i s a b 11 8 7 2 3d 0 0 8s s e r d d a d l e i f r e m o t s u c 12 8 7 2 3e 0 0 8s s e r d d a d l e i f r o d n e v 13 8 7 2 3f 0 0 84 8 7 2 30 1 0 8s s e r d d a d l e i f r o d n e v d e d n e t x e 15 8 7 2 31 1 0 8d e v r e s e r 16 8 7 2 32 1 0 8e p y t r e v i e c s n a r t 17 8 7 2 33 1 0 8e p y t r o t c e n n o c l a c i t p o 18 8 7 2 34 1 0 8g n i d o c n e t i b 19 8 7 2 35 1 0 80 9 7 2 36 1 0 8s / b m 1 f o s e l p i t l u m n i e t a r t i b l a n i m o n 11 9 7 2 37 1 0 8e p y t l o c o t o r p 12 9 7 2 38 1 0 81 0 8 2 31 2 0 80 e t y b e d o c e b g 0 1 s e d o c e c n a i l p m o c s d r a d n a t s 12 0 8 2 32 2 0 83 0 8 2 33 2 0 8s t n e m e r c n i m 0 1 n i e g n a r n o i s s i m s n a r t s e i f i c e p s 14 0 8 2 34 2 0 85 0 8 2 35 2 0 81 e t y b d n a 0 e t y b e p y t e r b i f 16 0 8 2 36 2 0 88 0 8 2 38 2 0 80 l e n n a h c - s p e t s m n 1 0 . 0 n i h t g n e l e v a w l a c i t p o e r t n e c 18 1 8 2 32 3 0 81 2 8 2 35 3 0 8i u o r e i f i t n e d i e g a k c a p 12 2 8 2 36 3 0 85 2 8 2 39 3 0 8i u o r o d n e v r e v i e c s n a r t
30 e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e r 16 2 8 2 3a 3 0 81 4 8 2 39 4 0 8i i c s a n i e m a n r o d n e v r e v i e c s n a r t 12 4 8 2 3a 4 0 87 5 8 2 39 5 0 8i i c s a n i r o d n e v r e v i e c s n a r t y b d e d i v o r p r e b m u n t r a p 18 5 8 2 3a 5 0 89 5 8 2 3b 5 0 8i i c s a r o d n e v y b d e d i v o r p r e b m u n t r a p r o f l e v e l n o i s i v e r 10 6 8 2 3c 5 0 85 7 8 2 3b 6 0 8i i c s a n i r e b m u n l a i r e s r o d n e v 16 7 8 2 3c 6 0 85 8 8 2 35 7 0 8i i c s a n i e d o c e t a d g n i r u t c a f u n a m r o d n e v 16 8 8 2 36 7 0 8e c n e r e f e r t n e m n o r i v n e d e s s e r t s v 5 17 8 8 2 37 7 0 8e c n e r e f e r t n e m n o r i v n e d e s s e r t s v 3 . 3 18 8 8 2 38 7 0 8e c n e r e f e r t n e m n o r i v n e d e s s e r t s s p a 19 8 8 2 39 7 0 8e g a t l o v s p a l a n i m o n 10 9 8 2 3a 7 0 8y t i l i b a p a c m o d 11 9 8 2 3b 7 0 8d e v r e s e r 13 9 8 2 3d 7 0 8m u s k c e h c d l e i f c i s a b 14 9 8 2 3e 7 0 81 4 9 2 3d a 0 8a e r a e l b a e t i r w r e m o t s u c 12 4 9 2 3e a 0 80 3 0 3 36 0 1 8c i f i c e p s r o d n e v 11 3 0 3 37 0 1 83 6 8 6 3f f f 8c i f i c e p s r o d n e v d e d n e t x e 14 6 8 6 30 0 0 9l o r t n o c m r a l a _ x r 15 6 8 6 31 0 0 9l o r t n o c m r a l a _ x t 16 6 8 6 32 0 0 9l o r t n o c i s a l 17 6 8 6 33 0 0 9s u t a t s m r a l a _ x r 18 6 8 6 34 0 0 9s u t a t s m r a l a _ x t 19 6 8 6 35 0 0 9s u t a t s i s a l 13 5 1 9 41 0 0 cs e r u t a e f a m p d e d n e t x e 15 5 1 9 43 0 0 cc i f i c e p s r o d n e v d m p / a m p 16 5 1 9 44 0 0 cm u s k c e h c c i f i c e p s r o d n e v d m p / a m p 18 8 1 9 44 2 0 cc i f i c e p s r o d n e v a m p
31 register 1.0 - pma/pmd control 1 register 1.1 - pma/pmd status 1 register 1.2 to 1.3 - device identifier register 1.4 pma/pmd speed ability note: 1. rw = read/write, ro = read only, ll = latching low ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 0 . 1t e s e rt e s e r d m p / a m p = 1 n o i t a r e p o l a m r o n = 0 w r 4 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 3 1 . 0 . 1n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r1 2 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 1 1 . 0 . 1r e w o p w o le d o m r e w o p w o l = 1 n o i t a r e p o l a m r o n = 0 w r0 7 : 0 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 6 . 0 . 1n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r1 2 : 5 . 0 . 1n o i t c e l e s d e e p s2 3 4 5 d e v r e s e r = x x x 1 d e v r e s e r = x x 1 x d e v r e s e r = x 1 x x d e v r e s e r = 1 0 0 0 s / b g 0 1 = 0 0 0 0 w r 1 . 0 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a s e u l a vw r 0 . 0 . 1k c a b p o o l a m pe d o m k c a b p o o l a m p e l b a n e = 1 e d o m k c a b p o o l a m p e l b a s i d = 0 w r0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 1 . 1d e v r e s e ra / no r 7 . 1 . 1t l u a fd m p / a m p n i d e t c e t e d n o i t i d n o c t l u a f l a c o l = 1 d m p / a m p n i d e t c e t e d t o n n o i t i d n o c t l u a f l a c o l = 0 ) e n o a o t t e s 0 1 . 8 . 1 r o 1 1 . 8 . 1 r e h t i e n e h w 1 a o t t e s ( o ra / n 3 : 6 . 1 . 1d e v r e s e ra / nl l / o r 2 . 1 . 1s u t a t s k n i l e v i e c e rl a n g i s e v i e c e r o t d e k c o l a m p = 1 l a n g i s e v i e c e r o t d e k c o l t o n a m p = 0 l l / o ra / n 1 . 1 . 1y t i l i b a n w o d r e w o pe d o m r e w o p w o l s t r o p p u s d m p / a m p = 1 e d o m r e w o p w o l t r o p p u s t o n s e o d d m p / a m p = 0 o r1 0 . 1 . 1d e v r e s e ra / n ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 3 . 1r e i f i t n e d i a m p o r 0 : 5 1 . 2 . 1r e i f i t n e d i a m p o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 : 5 1 . 4 . 1e r u t u f r o f d e v r e s e r s d e e p s o ra / n 0 . 4 . 1e l b a p a c g 0 1s / b g 0 1 t a g n i t a r e p o f o e l b a p a c s i d m p / a m p = 1 s / b g 0 1 t a g n i t a r e p o f o e l b a p a c t o n s i d m p / a m p = 0 o r1
32 register 1.5 to 1.6 - pma/pmd devices in package register 1.7 - 10 g pma/pmd control 2 note: 1. rw = read/write, ro = read only, ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 6 . 1e c i v e d c i f i c e p s r o d n e v t n e s e r p 2 e g a k c a p n i t n e s e r p 2 e c i v e d c i f i c e p s r o d n e v = 1 e g a k c a p n i t n e s e r p t o n 2 e c i v e d c i f i c e p s r o d n e v = 0 o r1 4 1 . 6 . 1c i f i c e p s r o d n e vd e v r e s e ro r 0 : 3 1 . 6 . 1d e v r e s e ra / no r 6 : 5 1 . 5 . 1d e v r e s e ra / no r 5 . 5 . 1t n e s e r p s x e t de g a k c a p n i t n e s e r p s x e t d = 1 e g a k c a p n i t n e s e r p t o n s x e t d = 0 o r0 4 . 5 . 1t n e s e r p s x y h pe g a k c a p n i t n e s e r p s x y h p = 1 e g a k c a p n i t n e s e r p t o n s x y h p = 0 o r1 3 . 5 . 1t n e s e r p s c pe g a k c a p n i t n e s e r p s c p = 1 e g a k c a p n i t n e s e r p t o n s c p = 0 o r1 2 . 5 . 1t n e s e r p s i we g a k c a p n i t n e s e r p s i w = 1 e g a k c a p n i t n e s e r p t o n s i w = 0 o r0 1 . 5 . 1t n e s e r p a m p / d m pe g a k c a p n i t n e s e r p a m p / d m p = 1 e g a k c a p n i t n e s e r p t o n a m p / d m p = 0 o r1 0 . 5 . 1s r e t s i g e r 2 2 e s u a l c t n e s e r p e g a k c a p n i t n e s e r p s r e t s i g e r 2 2 e s u a l c = 1 e g a k c a p n i t n e s e r p t o n s r e t s i g e r 2 2 e s u a l c = 0 o r0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 3 : 5 1 . 7 . 1d e v r e s e ra / n 0 : 2 . 7 . 1e p y t d m p / a m p n o i t c e l e s 0 1 2 e p y t d m p / a m p r s - e s a b g 0 1 = 1 1 1 e p y t d m p / a m p r l - e s a b g 0 1 = 0 1 1 e p y t d m p / a m p r e - e s a b g 0 1 = 1 0 1 e p y t d m p / a m p 4 x l - e s a b g 0 1 = 0 0 1 e p y t d m p / a m p w s - e s a b g 0 1 = 1 1 0 e p y t d m p / a m p w l - e s a b g 0 1 = 0 1 0 e p y t d m p / a m p w e - e s a b g 0 1 = 1 0 0 d e v r e s e r = 0 0 0 w r0 1 1
33 register 1.8 - 10 g pma/pma status 2 register 1.9 - 10 g pmd transmit disable note: 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exitsts following register read, the bit will not be cleared). ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 4 1 : 5 1 . 8 . 1t n e s e r p e c i v e d4 1 5 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d = 0 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 1 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 1 0 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 0 0 o r0 1 3 1 . 8 . 1t l u a f l a c o l t i m s n a r t y t i l i b a t l u a f l a c o l a t c e t e d o t y t i l i b a e h t s a h d m p / a m p = 1 h t a p t i m s n a r t e h t n o n o i t i d n o c t l u a f a t c e t e d o t y t i l i b a e h t e v a h t o n s e o d d m p / a m p = 0 h t a p t i m s n a r t e h t n o n o i t i d n o c o r1 2 1 . 8 . 1t l u a f l a c o l e v i e c e r y t i l i b a t l u a f l a c o l a t c e t e d o t y t i l i b a e h t s a h d m p / a m p = 1 h t a p e v i e c e r e h t n o n o i t i d n o c t l u a f a t c e t e d o t y t i l i b a e h t e v a h t o n s e o d d m p / a m p = 0 h t a p e v i e c e r e h t n o n o i t i d n o c o r1 1 1 . 8 . 1t l u a f l a c o l t i m s n a r th t a p t i m s n a r t n o n o i t i d n o c t l u a f l a c o l = 1 h t a p t i m s n a r t n o n o i t i d n o c t l u a f l a c o l o n = 0 h l / o ra / n 0 1 . 8 . 1t l u a f l a c o l e v i e c e rh t a p e v i e c e r n o n o i t i d n o c t l u a f l a c o l = 1 h t a p e v i e c e r n o n o i t i d n o c t l u a f l a c o l o n = 0 h l / o ra / n 9 . 8 . 1d e v r e s e ra / no r 8 . 8 . 1e l b a s i d t i m s n a r t d m p y t i l i b a h t a p t i m s n a r t e h t e l b a s i d o t y t i l i b a e h t s a h d m p = 1 t i m s n a r t e h t e l b a s i d o t y t i l i b a e h t e v a h t o n s e o d d m p = 0 h t a p o r1 7 . 8 . 1y t i l i b a r s - e s a b g 0 1r s - e s a b g 0 1 m r o f r e p o t e l b a s i d m p / a m p = 1 r s - e s a b g 0 1 m r o f r e p o t e l b a t o n s i d m p / a m p = 0 o r0 6 . 8 . 1y t i l i b a r l - e s a b g 0 1r l - e s a b g 0 1 m r o f r e p o t e l b a s i d m p / a m p = 1 r l - e s a b g 0 1 m r o f r e p o t e l b a t o n s i d m p / a m p = 0 o r1 5 . 8 . 1y t i l i b a r e - e s a b g 0 1r e - e s a b g 0 1 m r o f r e p o t e l b a s i d m p / a m p = 1 r e - e s a b g 0 1 m r o f r e p o t e l b a t o n s i d m p / a m p = 0 o r0 4 . 8 . 1y t i l i b a 4 x l - e s a b g 0 14 x l - e s a b g 0 1 m r o f r e p o t e l b a s i d m p / a m p = 1 4 x l - e s a b g 0 1 m r o f r e p o t e l b a t o n s i a m p / a m p = 0 o r0 3 . 8 . 1y t i l i b a w s - e s a b g 0 1w s - e s a b g 0 1 m r o f r e p o t e l b a s i d m p / a m p = 1 w s - e s a b g 0 1 m r o f r e p o t e l b a t o n s i d m p / a m p = 0 o r0 2 . 8 . 1y t i l i b a w l - e s a b g 0 1w s - e s a b g 0 1 m r o f r e p o t e l b a s i d m p / a m p = 1 w l - e s a b g 0 1 m r o f r e p o t e l b a t o n s i d m p / a m p = 0 o r0 1 . 8 . 1y t i l i b a w e - e s a b g 0 1w e - e s a b g 0 1 m r o f r e p o t e l b a s i d m p / a m p = 1 w e - e s a b g 0 1 m r o f r e p o t e l b a t o n s i d m p / a m p = 0 o r0 0 . 8 . 1y t i l i b a k c a b p o o l a m pn o i t c n u f k c a b p o o l a m r o f r e p o t y t i l i b a e h t s a h a m p = 1 k c a b p o o l a m r o f r e p o t y t i l i b a e h t e v a h t o n s e o d a m p = 0 n o i t c n u f o r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 : 5 1 . 9 . 1d e v r e s e ra / nw r 1 : 4 . 9 . 1t c e t e d l a n g i s 4 x ld e s u t o nw r0 0 : 4 . 9 . 1e l b a s i d t i m s n a r t d m pe l b a s i d t i m s n a r t = 1 e l b a n e t i m s n a r t = 0 w r0
34 register 1.10 - 10 g pmd receive signal ok register 1.14 to 1.15 - package identifier (oui) register 1.32768 - nvr control/status 1.32775 to 1.32782 - nvr information ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 : 5 1 . 0 1 . 1d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vo r 1 : 4 . 0 1 . 1t c e t e d l a n g i s 4 x ld e s u t o no r 0 . 0 1 . 1e v i e c e r d m p l a b o l g t c e t e d l a n g i s e v i e c e r n o d e t c e t e d l a n g i s = 1 e v i e c e r n o d e t c e t e d t o n l a n g i s = 0 o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 5 1 . 1d e v r e s e rd e v r e s e ro r8 4 2 1 1 : 4 1 . 5 1 . 1r e b m u n n o i s i v e rr e b m u n n o i s i v e ro r 8 : 1 1 . 5 1 . 1s s e r d d a r v ns s e r d d a v e d r v no r 6 : 7 . 5 1 . 1s s e r d d a r v ns s e r d d a v e d r v no r 0 : 5 . 5 1 . 1r e i f i t n e d i e g a k c a pi u o k a p n e xo r 8 : 5 1 . 4 1 . 1r e i f i t n e d i e g a k c a pi u o k a p n e xo r4 3 0 : 7 . 4 1 . 1r e i f i t n e d i e g a k c a pi u o k a p n e xo r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 8 6 7 2 3 . 1c i f i c e p s r o d n e v w r 6 : 7 . 8 6 7 2 3 . 1d e v r e s e ra / no r 5 . 8 6 7 2 3 . 1d n a m m o c e t i r w / d a e r 3 r v n d a e r = 0 r v n e t i r w = 1 w r 2 4 . 8 6 7 2 3 . 1d e v r e s e ra / no r 2 : 3 . 8 6 7 2 3 . 1s u t a t s d n a m m o ce l d i = 0 0 y l l u f s s e c c u s d e t e l p m o c d n a m m o c = 1 0 s s e r g o r p n i d n a m m o c = 0 1 d e l i a f d n a m m o c = 1 1 h l / o r 0 : 1 . 8 6 7 2 3 . 1s d n a m m o c d e d n e t x ed e v r e s e r = 0 0 d e v r e s e r = 1 0 e t y b 1 e t i r w / d a e r = 0 1 s t n e t n o c r v n l l a d a e r = 1 1 w r 2 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 5 7 7 2 3 . 1n o i s r e v) b s l : b s m ( r e b m u n n o i s r e v r v no r0 3 0 : 7 . 6 7 7 2 3 . 1e z i s _ r v ns e t y b 6 5 2 = ) e t y b r e p p u ( e z i s r v no r1 0 : 7 . 7 7 7 2 3 . 1e z i s _ r v ns e t y b 6 5 2 = ) e t y b r e w o l ( e z i s r v no r0 0 : 7 . 8 7 7 2 3 . 1d e s u _ m e ms e t y b 6 5 2 = ) e t y b r e p p u ( d e s u s e t y bo r1 0 : 7 . 9 7 7 2 3 . 1d e s u _ m e ms e t y b 6 5 2 = ) e t y b r e w o l ( d e s u s e t y bo r0 0 : 7 . 0 8 7 2 3 . 1r d d a c i s a bt r a t s ) b s l : b s m ( s s e r d d a d l e i f c i s a bo r1 1 0 : 7 . 1 8 7 2 3 . 1r d d a t s u ct r a t s ) b s l : b s m ( s s e r d d a d l e i f r e m o t s u co r9 1 1 0 : 7 . 2 8 7 2 3 . 1r d d a d n e vt r a t s ) b s l : b s m ( s s e r d d a d l e i f r o d n e vo r7 6 1 0 : 7 . 3 8 7 2 3 . 1r d d a d n e v t x et r a t s s s e r d d a d l e i f r o d n e v d e d n e t x eo r1 0 : 7 . 4 8 7 2 3 . 1r d d a d n e v t x et r a t s s s e r d d a d l e i f r o d n e v d e d n e t x eo r0 0 : 7 . 5 8 7 2 3 . 1d e v r e s e r o r0 note: 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared). 2. the values of the ?command? and ?extended command? bits are held until a command has been executed. 3. writes to register 1.32768 ignored during ?command in progress?. reads will not clear command status.
35 register 1.32786 - transceiver type register 1.32787 - optical connector type register 1.32788 - bit encoding register 1.32789 to 1.32790 - bit rate register 1.32791 - protocol type register 1.32792 to 1.32793 - 10gbe compliance code register 1.32802 to 1.32803 - transmission range register 1.32804 to 1.32805 - fiber type suitability register 1.32806 to 1.32808 - center wavelength note: 1. rw = read/write, ro = read only. ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 6 8 7 2 3 . 1e p y t r e v i e c s n a r tk a p n e xo r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 7 8 7 2 3 . 1r o t c e n n o cr o t c e n n o c x e l p u d c so r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 8 8 7 2 3 . 1g n i d o c n e t i bz r no r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 9 8 7 2 3 . 1e t a r t i b8 t i b o t ) b s m ( 5 1 t i bo r0 4 0 : 7 . 0 9 7 2 3 . 1e t a r t i b0 t i b o t 7 t i bo r2 7 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 1 9 7 2 3 . 1l o c o t o r pe b g 0 1 s t r o p p u so r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 2 9 7 2 3 . 1e c n a i l p m o c s d r a d n a t s e d o c r l - e s a b g 0 1 s t r o p p u so r2 0 : 5 1 . 3 9 7 2 3 . 1d e v r e s e ra / n0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 2 0 8 2 3 . 1e g n a r n o i s s i m s n a r t8 t i b o t ) b s m ( 5 1 t i bo r3 0 : 7 . 3 0 8 2 3 . 1e g n a r n o i s s i m s n a r t0 t i b o t 7 t i bo r2 3 2 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 5 . 4 0 8 2 3 . 1e p y t r e b i fc i r e n e g m so r2 3 0 . 5 0 8 2 3 . 1d e v r e s e ra / n0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 6 0 8 2 3 . 1h t g n e l e v a w6 1 - 3 2 s t i bo r1 0 : 7 . 7 0 8 2 3 . 1h t g n e l e v a w8 - 5 1 s t i bo r5 5 2 0 : 7 . 8 0 8 2 3 . 1h t g n e l e v a w0 - 7 s t i bo r4 8 1
36 register 1.32818 to 1.32821 - package identifier (oui) = xenpak register 1.32822 to 1.32825 - vendor (oui) = agilent register 1.32826 to 1.32841 - vendor name (ascii) note: 1. rw = read/write, ro = read only. ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 8 1 8 2 3 . 1r e i f i t n e d i e g a k c a pr e i f i t n e d i e g a k c a po r0 0 : 7 . 9 1 8 2 3 . 1r e i f i t n e d i e g a k c a pr e i f i t n e d i e g a k c a po r5 6 2 : 7 . 0 2 8 2 3 . 1r e i f i t n e d i e g a k c a pr e i f i t n e d i e g a k c a po r4 4 2 0 : 1 . 0 2 8 2 3 . 1s s e r d d a r v ns s e r d d a e c i v e d r v no r 5 : 7 . 1 2 8 2 3 . 1s s e r d d a r v ns s e r d d a e c i v e d r v no r2 3 1 : 4 . 1 2 8 2 3 . 1r e b m u n n o i s i v e rr e b m u n n o i s i v e ro r 0 . 1 2 8 2 3 . 1d e v r e s e rd e v r e s e r ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 2 2 8 2 3 . 1i u o r o d n e vi u o r o d n e vo r0 0 : 7 . 3 2 8 2 3 . 1i u o r o d n e vi u o r o d n e vo r1 5 2 : 7 . 4 2 8 2 3 . 1i u o r o d n e vi u o r o d n e vo r4 5 0 : 1 . 4 2 8 2 3 . 1o n l e d o mr e b m u n l e d o mo r 4 : 7 . 5 2 8 2 3 . 1o n l e d o mr e b m u n l e d o mo r0 0 : 3 . 5 2 8 2 3 . 1o n v e rr e b m u n n o i s i v e ro r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 6 2 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 5 1 e t y b e m a n r o d n e vo r) 5 6 ( a 0 : 7 . 7 2 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 4 1 e t y b e m a n r o d n e vo r) 1 7 ( g 0 : 7 . 8 2 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 3 1 e t y b e m a n r o d n e vo r) 3 7 ( i 0 : 7 . 9 2 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 2 1 e t y b e m a n r o d n e vo r) 6 7 ( l 0 : 7 . 0 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 1 1 e t y b e m a n r o d n e vo r) 9 6 ( e 0 : 7 . 1 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 0 1 e t y b e m a n r o d n e vo r) 8 7 ( n 0 : 7 . 2 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 9 e t y b e m a n r o d n e vo r) 4 8 ( t 0 : 7 . 3 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 8 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 4 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 7 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 5 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 6 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 6 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 5 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 7 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 4 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 8 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 3 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 9 3 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 2 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 0 4 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 1 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 1 4 8 2 3 . 1e m a n r o d n e v) b s l : b s m ( 0 e t y b e m a n r o d n e vo r) 2 3 ( e c a p s
37 register 1.32842 to 1.32857 - vendor part number (ascii) register 1.32858 to 1.32859 - vendor revision (ascii) register 1.32860 to 1.32875 - vendor serial number (ascii) note: 1. rw = read/write, ro = read only. ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 0 : 7 . 2 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 5 1 e t y b . o n t r a p r o d n e vo r) 2 7 ( h 0 : 7 . 3 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 4 1 e t y b . o n t r a p r o d n e vo r) 0 7 ( f 0 : 7 . 4 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 3 1 e t y b . o n t r a p r o d n e vo r) 7 6 ( c 0 : 7 . 5 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 2 1 e t y b . o n t r a p r o d n e vo r) 4 8 ( t 0 : 7 . 6 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 1 1 e t y b . o n t r a p r o d n e vo r) 5 4 ( - 0 : 7 . 7 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 0 1 e t y b . o n t r a p r o d n e vo r) 5 5 ( 7 0 : 7 . 8 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 9 e t y b . o n t r a p r o d n e vo r) 8 4 ( 0 0 : 7 . 9 4 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 8 e t y b . o n t r a p r o d n e vo r) 9 4 ( 1 0 : 7 . 0 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 7 e t y b . o n t r a p r o d n e vo r) 8 8 ( x 0 : 7 . 1 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 6 e t y b . o n t r a p r o d n e vo r) 6 6 ( b 0 : 7 . 2 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 5 e t y b . o n t r a p r o d n e vo r) 8 6 ( d 0 : 7 . 3 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 4 e t y b . o n t r a p r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 4 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 3 e t y b . o n t r a p r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 5 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 2 e t y b . o n t r a p r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 6 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 1 e t y b . o n t r a p r o d n e vo r) 2 3 ( e c a p s 0 : 7 . 7 5 8 2 3 . 1o n t r a p r o d n e v) b s l : b s m ( 0 e t y b . o n t r a p r o d n e vo r) 2 3 ( e c a p s ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) i i c s a ( e u l a v t l u a f e d 0 : 7 . 8 5 8 2 3 . 1v e r r o d n e v) b s l : b s m ( e t y b r e p p u n o i s i v e ro r8 4 0 : 7 . 9 5 8 2 3 . 1v e r r o d n e v) b s l : b s m ( e t y b r e w o l n o i s i v e ro r9 4 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 0 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 5 1 e t y b . o n l a i r e s r o d n e v 0 : 7 . 1 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 4 1 e t y b . o n l a i r e s r o d n e v 0 : 7 . 2 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 3 1 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 3 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 2 1 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 4 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 1 1 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 5 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 0 1 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 6 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 9 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 7 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 8 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 8 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 7 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 9 6 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 6 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 0 7 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 5 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 1 7 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 4 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 2 7 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 3 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 3 7 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 2 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 4 7 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 1 e t y b . o n l a i r e s r o d n e vo r- 0 : 7 . 5 7 8 2 3 . 1o n l a i r e s r o d n e v) b s l : b s m ( 0 e t y b . o n l a i r e s r o d n e vo r-
38 register 1.32876 to 1.32885 - date code (ascii) note: 1. rw = read/write, ro = read only. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 6 7 8 2 3 . 1) s ' 0 0 0 1 ( r a e y) b s l = 0 t i b , b s m = 7 t i b ( s ' 0 0 0 1 n i r a e y 0 : 7 . 7 7 8 2 3 . 1) s ' 0 0 1 ( r a e y) b s l = 0 t i b , b s m = 7 t i b ( s ' 0 0 1 n i r a e y 0 : 7 . 8 7 8 2 3 . 1) s ' 0 1 ( r a e y) b s l = 0 t i b , b s m = 7 t i b ( s ' 0 1 n i r a e yo r- 0 : 7 . 9 7 8 2 3 . 1) s ' 1 ( r a e y) b s l = 0 t i b , b s m = 7 t i b ( s t i n u r a e yo r- 0 : 7 . 0 8 8 2 3 . 1) s ' 0 1 ( h t n o m) b s l = 0 t i b , b s m = 7 t i b ( s ' 0 1 n i h t n o mo r- 0 : 7 . 1 8 8 2 3 . 1) s ' 1 ( h t n o m) b s l = 0 t i b , b s m = 7 t i b ( s t i n u n i h t n o mo r- 0 : 7 . 2 8 8 2 3 . 1) s ' 0 1 ( y a d) b s l = 0 t i b , b s m = 7 t i b ( s ' 0 1 n i y a do r- 0 : 7 . 3 8 8 2 3 . 1) s ' 1 ( y a d) b s l = 0 t i b , b s m = 7 t i b ( s t i n u n i y a do r- 0 : 7 . 4 8 8 2 3 . 1) s ' 0 1 ( e d o c t o l) b s l = 0 t i b , b s m = 7 t i b ( s ' 0 1 n i e d o c t o lo r- 0 : 7 . 5 8 8 2 3 . 1) s ' 1 ( e d o c t o l) b s l = 0 t i b , b s m = 7 t i b ( s t i n u n i e d o c t o lo r- ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 6 8 8 2 3 . 1y l p p u s v 5e c n e r e f e r t n e m n o r i v n e d e s s e r t s v 5o r0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 7 8 8 2 3 . 1y l p p u s v 3 . 3e c n e r e f e r t n e m n o r i v n e d e s s e r t s v 3 . 3o r2 3 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 8 8 8 2 3 . 1y l p p u s s p ae c n e r e f e r t n e m n o r i v n e d e s s e r t s s p ao r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 9 8 8 2 3 . 1e g a t l o v s p a) v 8 . 1 ( e g a t l o v s p a l a n i m o no r2 3 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 1 9 8 2 3 . 1s u t a t s / l o r t n o c m o ds u t a t s / l o r t n o c m o do r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 4 9 8 2 3 . 1a e r a e l b a e t i r w f o t r a t sa e r a e l b a e t i r w r e m o t s u c f o t r a t so r 0 : 7 . 1 4 9 2 3 . 1a e r a e l b a e t i r w f o d n ea e r a e l b a e t i r w r e m o t s u c f o d n eo r register 1.32886 - 5 v stressed environment register 1.32887 - 3.3 v stressed environment register 1.32888 - aps stressed environment register 1.32889 - aps voltage register 1.32890 - dom capability register 1.32891 - reversed register 1.32894 - 1.32941 customer writeable area ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 7 . 0 9 8 2 3 . 1s u t a t s: r e t s i g e r s u t a t s / l o r t n o c m o d d e t n e m e l p m i t o n = 0 d e t n e m e l p m i = 1 o r1 6 . 0 9 8 2 3 . 1t e s m o dd e t n e m e l p m i m o d n e h w t e so r1 5 . 0 9 8 2 3 . 1y t i l i b a p a c m d wt i b s i h t g n i t t e s : y t i l i b a p a c m o d e n a l y b e n a l m d w s i h t g n i t t e s . d i l a v e r a f f 0 a - o c 0 a s r e t s i g e r t a h t s e t a c i d n i f 6 0 a r e t s i g e r n i d e c a l p s n o i t a c i d n i e d i r r e v o t o n l l i w t i b ) y t i l i b a p a c m o d ( o r0 4 . 0 9 8 2 3 . 1e l a c s s a i b r e s a l: r o t c a f e l a c s s a i b r e s a l a 2 = 0 a 0 1 = 1 o r1 0 : 2 . 0 9 8 2 3 . 1m o d l a n r e t x ee c i v e d m o d l a n r e t x e f o s s e r d d ao r1 0 0
39 register 1.32942 to 1.33030 - vendor specific register 1.33030 - extended vendor specific register 1.36864 rx_alarm control (see also table 1.36867 rx_alarm status) register 1.36865 tx_alarm control (see also table 1.36868 tx_alarm status) ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 2 4 9 2 3 . 1 0 : 7 . 0 3 0 3 3 . 1 o t c i f i c e p s r o d n e vo r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 7 . 1 3 0 3 3 . 1c i f i c e p s r o d n e v d e d n e t x eo r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 1 : 5 1 . 4 6 8 6 3 . 1d e v r e s e rd e v r e s e ro r0 6 . 4 6 8 6 3 . 1r e f f u b e v i e c e r s x _ y h p e l b a n e r o r r e e l b a n e r o r r e w o l f r e d n u / r e v o r e f f u b e v i e c e r s x _ y h p = 1 d e l b a s i d = 0 w r0 5 . 4 6 8 6 3 . 1r e w o p l a c i t p o e v i e c e r t l u a f e l b a n e t l u a f r e w o p l a c i t p o e v i e c e r = 1 e l b a s i d t l u a f r e w o p l a c i t p o e v i e c e r = 0 4 . 4 6 8 6 3 . 1t l u a f l a c o l d m p / a m pe l b a n e t l u a f l a c o l r e v i e c e r d m p / a m p = 1 e l b a s i d t l u a f l a c o l r e v i e c e r d m p / a m p = 0 1 3 . 4 6 8 6 3 . 1t l u a f l a c o l s c pe l b a n e t l u a f l a c o l r e v i e c e r s c p = 1 e l b a s i d t l u a f l a c o l r e v i e c e r s c p = 0 w r1 2 . 4 6 8 6 3 . 1e d o c e v i e c e r s c pe l b a n e n o i t a l o i v = 1 e l b a s i d n o i t a l o i v = 0 1 . 4 6 8 6 3 . 1g a l f x rd e l b a n e = 1 d e l b a s i d = 0 w r0 0 . 4 6 8 6 3 . 1l a c o l e v i e c e r s x y h p t l u a f e l b a n e t l u a f l a c o l e v i e c e r s x y h p = 1 e l b a s i d t l u a f l a c o l e v i e c e r s x y h p = 0 w r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 1 : 5 1 . 5 6 8 6 3 . 1d e v r e s e rd e v r e s e ro r0 0 1 . 5 6 8 6 3 . 1n o i t a l o i v e d o c s x _ y h p r o r r e d e l b a n e r o r r e n o i t a l o i v e d o c s x _ y h p = 1 d e l b a s i d r o r r e n o i t a l o i v e d o c s x _ y h p = 0 w r3 e t o n 9 . 5 6 8 6 3 . 1t l u a f t n e r r u c s a i b r e s a le l b a n e t l u a f t n e r r u c s a i b r e s a l = 1 e l b a s i d t l u a f t n e r r u c s a i b r e s a l = 0 2 e t o n0 2 e t o n 8 . 5 6 8 6 3 . 1t l u a f p m e t r e s a le l b a n e t l u a f e r u t a r e p m e t r e s a l = 1 e l b a s i d t l u a f e r u t a r e p m e t r e s a l = 0 2 e t o n0 7 . 5 6 8 6 3 . 1t l u a f t u p t u o r e s a le l b a n e t l u a f r e w o p t u p t u o r e s a l = 1 e l b a s i d t l u a f r e w o p t u p t u o r e s a l = 0 2 e t o n0 6 . 5 6 8 6 3 . 1t l u a f r e t t i m s n a r te l b a n e t l u a f r e t t i m s n a r t = 1 e l b a s i d t l u a f r e t t i m s n a r t = 0 w r1 5 . 5 6 8 6 3 . 1f o s s o l r e t t i m s n a r t k c o l d e l b a n e k c o l f o s s o l r e t t i m s n a r t = 1 d e l b a s i d k c o l f o s s o l r e t t i m s n a r t = 0 w r3 e t o n 4 . 5 6 8 6 3 . 1t i m s n a r t d m p / a m p t l u a f e l b a n e t l u a f l a c o l r e t t i m s n a r t d m p / a m p = 1 e l b a s i d t l u a f l a c o l r e t t i m s n a r t d m p / a m p = 0 2 e t o n1 3 . 5 6 8 6 3 . 1t l u a f t i m s n a r t s c pe l b a n e t l u a f l a c o l t i m s n a r t s c p = 1 e l b a s i d t l u a f l a c o l t i m s n a r t s c p = 0 w r1 2 . 5 6 8 6 3 . 1r e f f u b s c p w o l f r e d n u / r e v o d e l b a n e w o l f r e d n u / r e v o r e f f u b s c p = 1 d e l b a s i d w o l f r e d n u / r e v o r e f f u b s c p = 0 w r0 1 . 5 6 8 6 3 . 1g a l f x td e l b a n e g a l f x t = 1 d e l b a s i d g a l f x t = 0 w r0 0 . 5 6 8 6 3 . 1t l u a f t i m s n a r t s x y h pe l b a n e t l u a f l a c o l t i m s n a r t s x y h p = 1 e l b a s i d t l u a f l a c o l t i m s n a r t s x y h p = 0 w r1 note: 1. rw = read/write, ro = read only. 2. optional features that are not implemented shall have their enable bit forced to zero. when implemented, the default value f or the control bit shall be 1. 3. the default value for a vendor specific bit shall be vendor specific.
40 register 1.36866 - lasi control (see also table 1.36869 lasi status) register 1.36867 - rx_alarm status (see also table 1.36864 - rx_alarm control) register 1.36868 - tx_alarm status (see also table 1.36865 tx_alarm control) ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 6 6 8 6 3 . 1d e v r e s e rd e v r e s e ro r0 6 . 6 6 8 6 3 . 1y l p p u s n i _ v 3 p 3 n o m w o l o o t w o l o o t y l p p u s f o n o i t c e t e d e l b a n e = 1 w o l o o t y l p p u s f o n o i t c e t e d e l b a s i d = 0 w r 5 . 6 6 8 6 3 . 1w o l o o t y l p p u s v 3 . 3w o l o o t y l p p u s f o n o i t c e t e d e l b a n e = 1 w o l o o t y l p p u s f o n o i t c e t e d e l b a s i d = 0 w r0 4 . 6 6 8 6 3 . 1w o l o o t y l p p u s v 8 . 1w o l o o t y l p p u s f o n o i t c e t e d e l b a n e = 1 w o l o o t y l p p u s f o n o i t c e t e d e l b a s i d = 0 w r0 3 . 6 6 8 6 3 . 1a t a d t s e t i s a la t a d t s e t i s a l e l b a n e = 1 a t a d t s e t i s a l e l b a s i d = 0 w r0 2 . 6 6 8 6 3 . 1m r a l a x re l b a n e m r a l a _ x r = 1 e l b a s i d m r a l a x r = 0 w r0 1 . 6 6 8 6 3 . 1m r a l a x te l b a n e m r a l a _ x t = 1 e l b a s i d m r a l a x t = 0 w r0 0 . 6 6 8 6 3 . 1m r a l a s le l b a n e m r a l a _ s l = 1 e l b a s i d m r a l a s l = 0 w r0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 1 : 5 1 . 7 6 8 6 3 . 1d e v r e s e rd e v r e s e rw r / o r 6 . 7 6 8 6 3 . 1r e f f u b e v i e c e r s x _ y h p e l b a n e r o r r e d e l b a n e w o l f r e d n u / r e v o r e f f u b e v i e c e r s x y h p = 1 d e l b a s i d w o l f r e d n u / r e v o r e f f u b e v i e c e r s x y h p = 0 h l / o r 5 . 7 6 8 6 3 . 1r e w o p l a c i t p o e v i e c e r t l u a f t l u a f r e w o p l a c i t p o n i d e t c e t e d n o i t i d n o c t l u a f l a c o lh l / o r 4 . 7 6 8 6 3 . 1e v i e c e r d m p / a m p t l u a f l a c o l ) 0 1 . 8 . 1 f o r o r r i m a ( t l u a f l a c o l e v i e c e r d m p / a m ph l / o r 3 . 7 6 8 6 3 . 1t l u a f l a c o l e v i e c e r s c p) 0 1 . 8 . 3 f o r o r r i m a ( t l u a f l a c o l e v i e c e r s c ph l / o r 2 . 7 6 8 6 3 . 1e d o c e v i e c e r s c p n o i t a l o i v n o i t a l o i v e d o c n i d e t c e t e d n o i t i d n o c t l u a f l a c o lh l / o r 1 . 7 6 8 6 3 . 1g a l f x r h l / o r 0 . 7 6 8 6 3 . 1l a c o l e v i e c e r s x - y h p t l u a f ) 0 1 . 8 . 4 f o r o r r i m a ( . t l u a f l a c o l e v i e c e r s x _ y h ph l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 1 : 5 1 . 8 6 8 6 3 . 1d e v r e s e rd e v r e s e ro r 0 1 . 8 6 8 6 3 . 1n o i t a l o i v e d o c s x _ y h p e l b a n e e l b a n e r o r r e n o i t a l o i v e d o c s x _ y h ph l / o r 9 . 8 6 8 6 3 . 1t l u a f s a i b r e s a l2 l e n n a h c c d a t l u a f t n e r r u c s a i b r e s a l h l / o r 8 . 8 6 8 6 3 . 1t l u a f p m e t r e s a l1 l e n n a h c c d a t l u a f e r u t a r e p m e t r e s a l h l / o r 7 . 8 6 8 6 3 . 1t l u a f r e w o p r e s a l0 l e n n a h c c d a t l u a f r e w o p t u p t u o r e s a l h l / o r 6 . 8 6 8 6 3 . 1t l u a f r e t t i m s n a r tt l u a f r e t t i m s n a r th l / o r 5 . 8 6 8 6 3 . 1k c o l f o s s o l r e t t i m s n a r t h l / o r 4 . 8 6 8 6 3 . 1t i m s n a r t d m p / a m p t l u a f l a c o l ) 1 1 . 8 . 1 o t d e k n i l ( t l u a f l a c o l r e t t i m s n a r t d m p / a m ph l / o r 3 . 8 6 8 6 3 . 1t l u a f l a c o l t i m s n a r t s c p) 1 1 . 8 . 3 o t d e k n i l ( t l u a f l a c o l t i m s n a r t s c ph l / o r 2 . 8 6 8 6 3 . 1r e f f u b s c p r o r r e w o l f r e d n u / r e v o 9 : 8 . 4 5 1 9 4 . 4 o t d e k n i lh l / o r 1 . 8 6 8 6 3 . 1g a l f _ x t h l / o r 0 . 8 6 8 6 3 . 1l a c o l t i m s n a r t s x y h p t l u a f ) 1 1 . 8 . 4 o t d e k n i l ( t l u a f l a c o l t i m s n a r t s x y h ph l / o r note: 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared).
41 register 1.36869 - lasi status (see also table 1.36866 lasi control) register 1.49153 - extended pma features notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. 2. the rx_alarm and tx_alarm indications are the logic or of the contents of registers 0x9003 and 0x9004 respectively. therefor e, these alarms will persist until the bit(s) reflecting the source of interrupt are cleared. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 7 : 5 1 . 9 6 8 6 3 . 1d e v r e s e rd e v r e s e ro r 6 . 9 6 8 6 3 . 1y l p p u s n i _ v 3 p 3 n o m m r a l a w o l o o t y l p p u s v 3 . 3 = 1 m r a l a o n = 0 h l / o r 5 . 9 6 8 6 3 . 1m r a l a y l p p u s v 3 . 3w o l o o t y l p p u s v 3 . 3 = 1 m r a l a o n = 0 h l / o r 4 . 9 6 8 6 3 . 1m r a l a y l p p u s v 8 . 1w o l o o t y l p p u s v 8 . 1 = 1 m r a l a o n = 0 h l / o r 3 . 9 6 8 6 3 . 1a t a d t s e t i s a la t a d t s e t n i d e t c e t e d n o i t i d n o c t l u a f l a c o lw r 2 . 9 6 8 6 3 . 1m r a l a _ x rm r a l a _ x r n i d e t c e t e d n o i t i d n o c t l u a f l a c o l = 1 m r a l a o n = 0 o r 2 1 . 9 6 8 6 3 . 1m r a l a _ x tm r a l a _ x t n i d e t c e t e d n o i t i d n o c t l u a f l a c o l = 1 m r a l a o n = 0 o r 2 0 . 9 6 8 6 3 . 1m r a l a _ s le g n a h c s u t a t s n i d e t c e t e d n o i t i d n o c t l u a f l a c o l = 1 e g n a h c s u t a t s o n = 0 h l ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 1 : 5 1 . 3 5 1 9 4 . 1d e v r e s e ra / n 0 1 . 3 5 1 9 4 . 1e d i r r e v o i _ b s o l x re d i r r e v o i _ b s o l x r = 1 e d i r r e v o o n = 0 w r0 9 . 3 5 1 9 4 . 1k c a b p o o l k r o w t e n a m p t u o a t a d k r o w t e n n i n e h w i u a x x r t a s e l d i l l a t i m s n a r t = 1 e d o m k c a b p o o l k c a b p o o l k r o w t e n n i n e h w i u a x x r t a a t a d e v i e c e r = 0 e d o m w r 5 : 8 . 3 5 1 9 4 . 1d e v r e s e ra / n 4 . 3 5 1 9 4 . 1k c a b p o o l k r o w t e n a m p e d o m k c a b p o o l k r o w t e n e l b a n e = 1 k c a b p o o l k r o w t e n e l b a s i d = 0 w r 3 . 3 5 1 9 4 . 1d e v r e s e ra / n 2 . 3 5 1 9 4 . 1n o m f e rt n e s e r p k l c f e r = 0o r1 1 . 3 5 1 9 4 . 1r r e _ n y sr o r r e e t a r k c o l c d e r e v o c e r = 1o r1 0 . 3 5 1 9 4 . 1k c o l x tk c o l n i l l p t i m s n a r t r e b i f = 1o r1
42 register 1.49155 - pma/pmd vendor specific register 1.49156 - pma/pmd vendor specific checksum register 1.49188 - pma vendor specific ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 4 1 : 5 1 . 5 5 1 9 4 . 1e d o m t s e t m o r p e ez h k 7 3 = 0 0 e d o m t s e t y c n e u q e r f h g i h = 1 0 e s u t o n o d - e d o m g u b e d = 0 1 e s u t o n o d - e d o m g u b e d = 1 1 w r 3 1 . 5 5 1 9 4 . 1t c e t e d m o r p e ed e t c e t e d = 1o r 2 1 . 5 5 1 9 4 . 1r o r r e m o r p e er o r r e m o r p e e = 1h l / o r 1 1 . 5 5 1 9 4 . 1e v i t c a m o r p e eo t s e t i r w o i d m , s s e r g o r p n i s s e c c a m o r p e e = 1 d e r o n g i s r e t s i g e r m o r p e e o r 8 : 0 1 . 5 5 1 9 4 . 1d e v r e s e r o r 7 . 5 5 1 9 4 . 1k o m u s k c e h c m o r p e ek o = 1h l / o r 6 . 5 5 1 9 4 . 1d e v r e s e r o r 4 : 5 . 5 5 1 9 4 . 1d a e r e t y b 6 5 2 m o r p e e e z i s t s r u b e l c y c 0 t i b 1 t i b e z i s 0 0 1 1 0 8 0 1 6 1 1 1 6 5 2 w r1 1 2 : 3 . 5 5 1 9 4 . 1d e v r e s e r o r 0 : 1 . 5 5 1 9 4 . 1e t i r w e t y b 6 5 2 m o r p e e e z i s t s r u b e l c y c 0 t i b 1 t i b e z i s 0 0 1 1 0 8 0 1 6 1 1 1 1 w r1 0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 6 5 1 9 4 . 1d e t a l u c l a c m o r p e e m u s k c e h c o r 4 : 7 . 6 5 1 9 4 . 1d e v r e s e r o r 2 : 3 . 6 5 1 9 4 . 1e t i r w e t y b 6 5 2 m o r p e e e z i s t s r u b e l c y c 0 t i b 1 t i b e z i s 0 0 1 1 0 8 0 1 6 1 1 1 1 w r1 0 0 : 1 . 6 5 1 9 4 . 1d n a m m o c e t i r w m o dd n a m m o c 0 t i b 1 t i b d e v r e s e r 0 0 d e v r e s e r 1 0 d e v r e s e r 0 1 s e t y b 6 5 2 e t i r w 1 1 w r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 4 : 5 1 . 8 8 1 9 4 . 1d e v r e s e r o r 3 . 8 8 1 9 4 . 1y c n e u q e r f t u o l l p x t n o i t c e l e s z h g 0 1 = 1 z h m 6 5 1 = 0 w r0 2 . 8 8 1 9 4 . 1d e v r e s e r o r 1 . 8 8 1 9 4 . 1e l b a n e t u o l l p x td e l b a n e = 1 d e l b a s i d = 0 w r0 0 . 8 8 1 9 4 . 1e t a t s i r t l c s _ m o r p e ee t a t s i r t = 1 e t a t s i r t t o n = 0 w r0 notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared.
43 HFCT-701XBD device 3 pcs registers e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e r 30 0 1 l o r t n o c s c p 31 1 1 s u t a t s s c p 32 2 3 3 r e i f i t n e d i e c i v e d s c p 34 4 y t i l i b a d e e p s s c p 35 5 6 6 e g a k c a p n i s e c i v e d s c p 37 7 2 l o r t n o c s c p g 0 1 38 8 2 s u t a t s s c p g 0 1 32 30 21 s u t a t s s c p r - e s a b g 0 1 33 31 22 s u t a t s s c p r - e s a b g 0 1 34 32 27 35 2a d e e s n r e t t a p t s e t s c p r - e s a b g 0 1 38 36 21 49 2b d e e s n r e t t a p t s e t s c p r - e s a b g 0 1 32 4a 2l o r t n o c n r e t t a p t s e t s c p r - e s a b g 0 1 33 4b 2 r e t n u o c r o r r e n r e t t a p t s e t s c p r - e s a b g 0 1 3 3 32 5 1 9 40 0 0 cs e r u t a e f d e d n e t x e s c p 33 5 1 9 41 0 0 0 c7 5 1 9 45 0 0 c 38 5 1 9 46 0 0 c9 6 1 9 41 1 0 cc i f i c e p s r o d n e v s c p
44 register 3.0 - pcs control 1 register 3.1 - pcs status 1 register 3.2 to 3.3 - pcs device identifier a mirror of registers 1.2 to 1.3. register 3.4 - pcs speed ability register 3.5 to 3.6 - pcs devices in package a mirror of registers 1.5 to 1.6. note: 1. rw = read/write, sc = self clearing, ro = read only, ll = latching low. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 0 . 3t e s e r 6 6 / 4 6 s c pt e s e r s c p = 1 n o i t a r e p o l a m r o n = 0 c s / w r 4 1 . 0 . 3k c a b p o o l s c pe d o m k c a b p o o l e l b a n e = 1 e d o m k c a b p o o l e l b a s i d = 0 w r0 3 1 . 0 . 3n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r 2 1 . 0 . 3d e v r e s e r w r 1 1 . 0 . 3r e w o p w o le d o m r e w o p w o l = 1 n o i t a r e p o l a m r o n = 0 w r 7 : 0 1 . 0 . 3d e v r e s e r w r 6 . 0 . 3n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r 2 : 5 . 0 . 3n o i t c e l e s d e e p s2 3 4 5 s / b g 0 1 = 0 0 0 0 w r0 0 0 0 0 : 1 . 0 . 3d e v r e s e r w r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 1 . 3d e v r e s e r o r 7 . 1 . 3t l u a f l a c o ld e t c e t e d n o i t i d n o c t l u a f l a c o l = 1 d e t c e t e d t o n n o i t i d n o c t l u a f l a c o l = 0 ) 1 o t t e s 0 1 . 8 . 3 r o 1 1 . 8 . 3 r e h t i e n e h w 1 o t t e s ( o r 3 : 6 . 1 . 3d e v r e s e ra / n 2 . 1 . 3s u t a t s k n i l e v i e c e r s c pp u k n i l e v i e c e r s c p = 1 n w o d k n i l e v i e c e r s c p = 0 l l / o r 1 . 1 . 3y t i l i b a r e w o p w o le d o m r e w o p w o l s t r o p p u s s c p = 1 e d o m r e w o p w o l t r o p p u s t o n s e o d s c p = 0 o r 0 . 1 . 3d e v r e s e ra / no r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 : 5 1 . 4 . 3d e v r e s e r o ra / n 0 . 4 . 3e l b a p a c g 0 1s / b g 0 1 t a g n i t a r e p o f o e l b a p a c s c p = 1 s / b g 0 1 t a g n i t a r e p o f o e l b a p a c t o n s i s c p = 0 o r1
45 register 3.7 - 10 g pcs control 2 register 3.8 - 10 g pcs status 2 register 3.32 - 10gbase-r pcs status 1 notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 2 : 5 1 . 7 . 3d e v r e s e ra / n 0 : 1 . 7 . 3n o i t c e l e s e p y t s c p0 1 e p y t s c p r - e s a b g 0 1 t c e l e s = 0 0 w r0 0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 4 1 : 5 1 . 8 . 3t n e s e r p e c i v e d4 1 5 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d = 0 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 1 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 1 0 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 0 0 o r 2 1 : 3 1 . 8 . 3d e v r e s e ra / no r 1 1 . 8 . 3t l u a f l a c o l t i m s n a r th t a p t i m s n a r t n o n o i t i d n o c t l u a f l a c o l = 1 h t a p t i m s n a r t n o n o i t i d n o c t l u a f l a c o l o n = 0 h l / o r 0 1 . 8 . 3t l u a f l a c o l e v i e c e rh t a p e v i e c e r n o n o i t i d n o c t l u a f l a c o l = 1 h t a p e v i e c e r n o n o i t i d n o c t l u a f l a c o l o n = 0 h l / o r 3 : 9 . 8 . 3d e v r e s e ra / no r 2 . 8 . 3e l b a p a c w - e s a b g 0 1e p y t s c p w - e s a b g 0 1 t r o p p u s o t e l b a s i s c p = 1 e p y t s c p w - e s a b g 0 1 t r o p p u s o t e l b a t o n s i s c p = 0 o r 1 . 8 . 3e l b a p a c x - e s a b g 0 1e p y t s c p x - e s a b g 0 1 t r o p p u s o t e l b a s i s c p = 1 e p y t s c p x - e s a b g 0 1 t r o p p u s o t e l b a t o n s i s c p = 0 o r 0 . 8 . 3e l b a p a c r - e s a b g 0 1e p y t s c p r - e s a b g 0 1 t r o p p u s o t e l b a s i s c p = 1 e p y t s c p r - e s a b g 0 1 t r o p p u s o t e l b a t o n s i s c p = 0 o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 3 1 : 5 1 . 2 3 . 3d e v r e s e r o r 2 1 . 2 3 . 3k n i l e v i e c e r r - e s a b g 0 1 s u t a t s p u k n i l e v i e c e r s c p r - e s a b g 0 1 = 1 n w o d k n i l e v i e c e r s c p r - e s a b g 0 1 = 0 o r 3 : 1 1 . 2 3 . 3d e v r e s e r o r 2 . 2 3 . 3g n i t s e t n r e t t a p 1 3 s b r p y t i l i b a g n i t s e t n r e t t a p 1 3 s b r p t r o p p u s o t e l b a s i s c p = 1 g n i t s e t n r e t t a p 1 3 s b r p t r o p p u s o t e l b a t o n s i s c p = 0 o r 1 . 2 3 . 3h g i h s c p r - e s a b g 0 1 r e b r e b h g i h a g n i t r o p e r s c p r - e s a b g 0 1 = 1 r e b h g i h a g n i t r o p e r t o n s c p r - e s a b g 0 1 = 0 o r 0 . 2 3 . 3k c o l b s c p r - e s a b g 0 1 k c o l s k c o l b d e v i e c e r o t d e k c o l s c p r - e s a b g 0 1 = 1 s k c o l b d e v i e c e r o t d e k c o l t o n s c p r - e s a b g 0 1 = 0 o r
46 register 3.33 - 10gbase-r pcs status 2 register 3.34 to 3.37 - 10gbase-r pcs test pattern seed a register 3.38 to 3.41 - 10gbase-r pcs test pattern seed b register 3.42 - 10gbase-r pcs test pattern control notes : 1. rw = read/write, ro = read only, ll = latching low, lh = latch high, clear on read (note that if the condition exists followi ng register read, the bit will not be cleared, nr = non roll-over. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 3 3 . 3k c o l k c o l b d e h c t a ld a e r t s a l e c n i s k c o l k c o l b d e t r o p e r s a h s c p = 1 d a e r t s a l e c n i s k c o l k c o l b d e t r o p e r t o n s a h s c p = 0 l l / o r 4 1 . 3 3 . 3r e b h g i h d e h c t a ld a e r t s a l e c n i s r e b h g i h d e t r o p e r s a h s c p = 1 d a e r t s a l e c n i s r e b h g i h d e t r o p e r t o n s a h s c p = 0 h l / o r 8 : 3 1 . 3 3 . 3r e br e t n u o c r e br n / o r 0 : 7 . 3 3 . 3s k c o l b d e r o r r er e k c e h c n r e t t a p r e t t i jr n / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 1 : 5 1 . 7 3 . 3d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 0 : 9 . 7 3 . 33 a d e e s n r e t t a p t s e t7 5 - 8 4 s t i b a d e e s n r e t t a p t s e tw r 0 : 5 1 . 6 3 . 32 a d e e s n r e t t a p t s e t7 4 - 2 3 s t i b a d e e s n r e t t a p t s e tw r 0 : 5 1 . 5 3 . 31 a d e e s n r e t t a p t s e t1 3 - 6 1 s t i b a d e e s n r e t t a p t s e tw r 0 : 5 1 . 4 3 . 30 a d e e s n r e t t a p t s e t5 1 - 0 s t i b a d e e s n r e t t a p t s e tw r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 1 : 5 1 . 1 4 . 3d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 0 : 9 . 1 4 . 33 b d e e s n r e t t a p t s e t7 5 - 8 4 s t i b b d e e s n r e t t a p t s e tw r 0 : 5 1 . 0 4 . 32 b d e e s n r e t t a p t s e t7 4 - 2 3 s t i b b d e e s n r e t t a p t s e tw r 0 : 5 1 . 9 3 . 31 b d e e s n r e t t a p t s e t1 3 - 6 1 s t i b b d e e s n r e t t a p t s e tw r 0 : 5 1 . 8 3 . 30 b d e e s n r e t t a p t s e t5 1 - 0 s t i b b d e e s n r e t t a p t s e tw r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 6 : 5 1 . 2 4 . 3d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r 5 . 2 4 . 3t s e t e v i e c e r 1 3 s b r p n r e t t a p e v i e c e r e h t n o e d o m n r e t t a p t s e t 1 3 s b r p e l b a n e = 1 h t a p e v i e c e r e h t n o e d o m n r e t t a p t s e t 1 3 s b r p e l b a s i d = 0 h t a p w r0 4 . 2 4 . 3t s e t t i m s n a r t 1 3 s b r p n r e t t a p t i m s n a r t e h t n o e d o m n r e t t a p t s e t 1 3 s b r p e l b a n e = 1 h t a p t i m s n a r t e h t n o e d o m n r e t t a p t s e t 1 3 s b r p e l b a s i d = 0 h t a p w r0 3 . 2 4 . 3n r e t t a p t s e t t i m s n a r tg n i t s e t n r e t t a p t s e t t i m s n a r t e l b a n e = 1 g n i t s e t n r e t t a p t s e t t i m s n a r t e l b a s i d = 0 w r 2 . 2 4 . 3n r e t t a p t s e t e v i e c e rg n i t s e t n r e t t a p t s e t e v i e c e r e l b a n e = 1 g n i t s e t n r e t t a p t s e t e v i e c e r e l b a s i d = 0 w r 1 . 2 4 . 3t c e l e s n r e t t a p t s e tn r e t t a p t s e t e v a w e r a u q s = 1 n r e t t a p t s e t m o d n a r o d u e s p = 0 w r 0 . 2 4 . 3t c e l e s n r e t t a p a t a dn r e t t a p a t a d s o r e z = 1 n r e t t a p a t a d f l = 0 w r
47 register 3.43 - 10gbase-r pcs test pattern error counter register 3.49152 - pcs extended features notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared, nr = non roll-over. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 3 4 . 3r o r r e n r e t t a p t s e t r e t n u o c r e t n u o c r o r r e 0 t i b = b s l 5 1 t i b = b s m r n / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 2 5 1 9 4 . 3r e t s i g e r c i t s o n g a i dr e t s i g e r c i t s o n g a i do r 6 : 7 . 2 5 1 9 4 . 3d e v r e s e ra / n 5 . 2 5 1 9 4 . 3t u o a t a d k c a b p o o l s c pe d o m k c a b p o o l s c p n i n e h w t u o x t t a a t a d t i m s n a r t = 1 e d o m k c a b p o o l s c p n i n e h w e v a w e r a u q s a t i m s n a r t = 0 w r0 4 . 2 5 1 9 4 . 3s c p t i m s n a r t t e s e rt e s e r t o n = 1 g n i r a e l c f l e s t o n : e t o n t e s e r = 0 w r1 3 . 2 5 1 9 4 . 3s c p e v i e c e r t e s e rt e s e r t o n = 1 g n i r a e l c f l e s t o n : e t o n t e s e r = 0 w r1 2 . 2 5 1 9 4 . 3s s a p y b r e l b m a r c s x ts s a p y b = 1w r0 1 . 2 5 1 9 4 . 3s s a p y b r e l b m a r c s x rs s a p y b = 1w r0 0 . 2 5 1 9 4 . 3r o r r e r e d o c n e 6 6 / 4 6r o r r e = 1h l / o r0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 7 : 5 1 . 8 5 1 9 4 . 3c i f i c e p s r o d n e vt n u o c r o r r e s b r p r e b i fo r 0 : 6 . 8 5 1 9 4 . 3t e s f f o e m a r f e v i e c e r o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 9 5 1 9 4 . 3i i m g x f o s t i b 6 1 t s r i f g a l f r o r r e s u b n o i t a c o l t i b s i h t t a r o r r e = 1h l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 0 6 1 9 4 . 3f o s t i b 6 1 d n o c e s g a l f r o r r e s u b i i m g x n o i t a c o l t i b s i h t t a r o r r e = 1h l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 6 : 5 1 . 1 6 1 9 4 . 3c i f i c e p s r o d n e vd e v r e s e ro r 5 . 1 6 1 9 4 . 3g a l f _ r r e _ e l d i _ x rs r o r r e e l d i r o t r a t s h t i w t u b t e k c a p l l u f a d e v i e c e rh l / o r 4 . 1 6 1 9 4 . 3g a l f _ r r e _ t r a t s _ x rs r o r r e e l b m a e r p h t i w t u b r e k c a p l l u f a d e v i e c e rh l / o r 3 . 1 6 1 9 4 . 3g a l f _ r r e _ a t a d _ x rt e k c a p g n o l t u b t e k c a p l l u f a d e v i e c e rh l / o r 2 . 1 6 1 9 4 . 3g a l f _ t k p _ g n o l _ x rt e k c a p g n o l t u b t e k c a p l l u f a d e v i e c e rh l / o r 1 . 1 6 1 9 4 . 3g a l f _ t k p _ t r o h s _ x rt e k c a p t r o h s t u b t e k c a p l l u f a d e v i e c e rh l / o r 0 . 1 6 1 9 4 . 3g a l f _ r r e _ m r e t _ x re l d i n a t o n s i e t y b t x e n e h t t u b d e v i e c e r e t a n i m r e t f i t e sh l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 3 5 1 9 4 . 3 0 : 5 1 . 4 5 1 9 4 . 3 0 : 5 1 . 5 5 1 9 4 . 3 0 : 5 1 . 6 5 1 9 4 . 3 0 : 5 1 . 7 5 1 9 4 . 3 s r e t s i g e r c i t s o n g a i d register 3.49153 - 3.49157 - pcs vendor specific register 3.49158 - pcs vendor specific register 3.49159 - pcs vendor specific receive path packet checker register 3.49160 - pcs vendor specific receive path packet checker register 3.49161 - pcs vendor specific receive path packet checker status
48 register 3.49162 - pcs vendor specific transmit path packet checker register 3.49163 - pcs vendor specific transmit path packet checker register 3.49164 - pcs vendor specific packet generator/checker register 3.49165 - pcs vendor specific packet generator register 3.49166 - pcs vendor specific packet generator register 3.49167 - pcs vendor specific packet generator notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 2 6 1 9 4 . 3i i m g x f o s t i b 6 1 t s r i f g a l f r o r r e s u b n o i t a c o l t i b s i h t t a r o r r e = 1h l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 3 6 1 9 4 . 3f o s t i b 6 1 d n o c e s g a l f r o r r e s u b i i m g x n o i t a c o l t i b s i h t t a r o r r e = 1h l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 6 : 5 1 . 4 6 1 9 4 . 3e l d i r o t a r e n e g t e k c a p e z i s w r 5 . 4 6 1 9 4 . 3g a l f _ r r e _ e l d i _ x ts r o r r e e l d i r o t r a t s h t i w t u b t e k c a p l l u f a d e v i e c e rh l / o r 4 . 4 6 1 9 4 . 3g a l f _ r r e _ t r a t s _ x ts r o r r e e l b m a e r p h t i w t u b t e k c a p l l u f a d e v i e c e rh l / o r 3 . 4 6 1 9 4 . 3g a l f _ r r e _ a t a d _ x tt e k c a p g n o l h t i w t u b t e k c a p l l u f a d e v i e c e rh l / o r 2 . 4 6 1 9 4 . 3g a l f _ t k p _ g n o l _ x tt e k c a p g n o l h t i w t u b t e k c a p l l u f a d e v i e c e rh l / o r 1 . 4 6 1 9 4 . 3g a l f _ t k p _ t r o h s _ x tt e k c a p t r o h s h t i w t u b t e k c a p l l u f a d e v i e c e rh l / o r 0 . 4 6 1 9 4 . 3g a l f _ r r e _ m r e t _ x te l d i n a t o n s i e t y b t x e n e h t t u b d e v i e c e r e t a n i m r e t f i t e sh l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 5 6 1 9 4 . 3n r e t t a p d e x i fi i m g x f o s t i b 6 1 t s r i fw r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 6 6 1 9 4 . 3n r e t t a p d e x i fi i m g x f o s t i b 6 1 d n o c e sw r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 4 1 : 5 1 . 7 6 1 9 4 . 3c i f i c e p s r o d n e vd e v r e s e ro r 3 1 . 7 6 1 9 4 . 3r e k c e h c n r e t t a p h t a p x td e l b a n e = 1 d e l b a s i d = 0 w r0 2 1 . 7 6 1 9 4 . 3n r e t t a p h t a p x t r o t a r e n e g d e l b a n e = 1 d e l b a s i d = 0 w r0 1 1 . 7 6 1 9 4 . 3r e k c e h c n r e t t a p h t a p x rd e l b a n e = 1 d e l b a s i d = 0 w r0 0 1 . 7 6 1 9 4 . 3n r e t t a p h t a p x r r o t a r e n e g d e l b a n e = 1 d e l b a s i d = 0 w r0 9 . 7 6 1 9 4 . 3e p y t t e k c a pn r e t t a p t n e m e r c n i = 1 n r e t t a p d e x i f = 0 w r 0 : 8 . 7 6 1 9 4 . 3e z i s t e k c a p a t a d 4 y b d e d i v i d w r
49 register 3.49169 - pcs vendor specific note: 1. rw = read/write, ro = read only. HFCT-701XBD device 4 phyxs registers ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 2 : 5 1 . 9 6 1 9 4 . 3d e v r e s e r o r 1 . 9 6 1 9 4 . 3r o r r e o f i f x o b r a e gr e t s i g e r c i t s o n g a i do r 0 . 9 6 1 9 4 . 3r o r r e o f i f c n y s e m a r fr e t s i g e r c i t s o n g a i do r e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e r 40 0 1 l o r t n o c s x y h p 41 1 1 s u t a t s s x y h p 42 2 3 3 r e i f i t n e d i e c i v e d s x y h p 44 4 y t i l i b a d e e p s s x y h p 45 5 6 6 e g a k c a p n i s e c i v e d s x y h p 48 8 2 s u t a t s s x y h p 44 1e 5 1f r e i f i t n e d i e g a k c a p s x y h p 44 28 1s u t a t s e n a l s x g x y h p g 0 1 45 29 1l o r t n o c t s e t s x g x y h p g 0 1 42 5 1 9 40 0 0 cs e r u t a e f d e d n e t x e s x _ y h p 43 5 1 9 41 0 0 cs e r u t a e f d e d n e t x e s x _ y h p 44 5 1 9 42 0 0 c0 6 1 9 48 0 0 cc i f i c e p s r o d n e v s x _ y h p
50 register 4.0 - phy_xs control 1 register 4.1 - phy_xs status 1 register 4.2 to 4.3 - device identifier a mirror of registers 1.2 to 1.3. register 4.4 - phy_xs speed ability register 4.5 to 4.6 - device in package a mirror of registers 1.5 to 1.6. notes : 1. rw = read/write, sc = self clearing, ro = read only, ll = latching low. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 0 . 4t e s e r l a b o l gt e s e r = 1 n o i t a r e p o l a m r o n = 0 c s / w r 4 1 . 0 . 4k c a b p o o le d o m k c a b p o o l s x y h p e l b a n e = 1 e d o m k c a b p o o l s x y h p e l b a s i d = 0 w r0 3 1 . 0 . 4n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r 2 1 . 0 . 4d e v r e s e r w r 1 1 . 0 . 4r e w o p w o le d o m r e w o p w o l = 1 n o i t a r e p o l a m r o n = 0 w r 7 : 0 1 . 0 . 4d e v r e s e r w r 6 . 0 . 4n o i t c e l e s d e e p se v o b a d n a s / b g 0 1 t a n o i t a r e p o = 1 d e i f i c e p s n u = 0 w r 2 : 5 . 0 . 4n o i t c e l e s d e e p s2 3 4 5 s / b g 0 1 = 0 0 0 0 w r0 0 0 0 0 : 1 . 0 . 4d e v r e s e rd e r o n g i s e t i r w , 0 s y a w l a e u l a vw r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 1 . 4d e v r e s e ra / no r 7 . 1 . 4t l u a f l a c o ls x y h p n o d e t c e t e d n o i t i d n o c t l u a f l a c o l = 1 s x y h p n o d e t c e t e d t o n n o i t i d n o c t l u a f l a c o l = 0 o r 3 : 6 . 1 . 4d e v r e s e ra / no r 2 . 1 . 4k n i l t i m s n a r t s x y h p s u t a t s p u s i k n i l t i m s n a r t s x y h p e h t = 1 n w o d s i k n i l t i m s n a r t s x y h p e h t = 0 l l / o r 1 . 1 . 4y t i l i b a r e w o p w o le d o m r e w o p w o l s t r o p p u s s x y h p = 1 e d o m r e w o p w o l t r o p p u s t o n s e o d s x y h p = 0 o r1 0 . 1 . 4d e v r e s e ra / no r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 1 : 5 1 . 4 . 4e r u t u f r o f d e v r e s e r s d e e p s o r 0 . 4 . 4e l b a p a c g 0 1s / b g 0 1 t a g n i t a r e p o f o e l b a p a c s i s x y h p = 1 s / b g 0 1 t a g n i t a r e p o f o e l b a p a c t o n s i s x y h p = 0 o r1
51 register 4.8 - phy_xs status 2 register 4.14 to 4.15 - package identifier (oui) a mirror of registers 1.32818 to 1.32821. register 4.24 - 10g phy_xgxs lane status register 4.25 - 10 g phy_xgxs test control notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 4 1 : 5 1 . 8 . 4t n e s e r p e c i v e d4 1 5 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d = 0 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 1 1 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 1 0 s s e r d d a s i h t t a g n i d n o p s e r e c i v e d o n = 0 0 o r0 1 2 1 : 3 1 . 8 . 4d e v r e s e ra / n 1 1 . 8 . 4t l u a f l a c o l t i m s n a r ts x y h p f o h t a p t i m s n a r t n o n o i t i d n o c t l u a f l a c o l = 1 s x y h p f o h t a p t i m s n a r t n o n o i t i d n o c t l u a f l a c o l o n = 0 h l / o r 0 1 . 8 . 4t l u a f l a c o l e v i e c e rs x y h p f o h t a p e v i e c e r n o n o i t i d n o c t l u a f = 1 s x y h p f o h t a p e v i e c e r n o n o i t i d n o c t l u a f o n = 0 h l / o r 0 : 9 . 8 . 4d e v r e s e ra / no r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 3 1 : 5 1 . 4 2 . 4d e v r e s e ra / no r 2 1 . 4 2 . 4e n a l s x g x y h p s u t a t s t n e m n g i l a d e n g i l a s e n a l t i m s n a r t s x g x y h p = 1 d e n g i l a t o n s e n a l t i m s n a r t s x g x y h p = 0 o r 1 1 . 4 2 . 4y t i l i b a g n i t s e t n r e t t a ps n r e t t a p t s e t e t a r e n e g o t e l b a s i s x g x y h p = 1 s n r e t t a p t s e t e t a r e n e g o t e l b a t o n s i s x g x y h p = 0 o r1 0 1 . 4 2 . 4k c a b p o o l s x g x y h p y t i l i b a k c a b p o o l a m r o f r e p o t y t i l i b a e h t s a h s x g x y h p = 1 n o i t c n u f a m r o f r e p o t y t i l i b a e h t e v a h t o n s e o d s x g x y h p = 0 n o i t c n u f k c a b p o o l o r1 4 : 9 . 4 2 . 4d e v r e s e ra / no r 3 . 4 2 . 4c n y s 3 e n a ld e z i n o r h c n y s s i 3 e n a l = 1 d e z i n o r h c n y s t o n s i 3 e n a l = 0 o ra / n 2 . 4 2 . 4c n y s 2 e n a ld e z i n o r h c n y s s i 2 e n a l = 1 d e z i n o r h c n y s t o n s i 2 e n a l = 0 o ra / n 1 . 4 2 . 4c n y s 1 e n a ld e z i n o r h c n y s s i 1 e n a l = 1 d e z i n o r h c n y s t o n s i 1 e n a l = 0 o ra / n 0 . 4 2 . 4c n y s 0 e n a ld e z i n o r h c n y s s i 0 e n a l = 1 d e z i n o r h c n y s t o n s i 0 e n a l = 0 o ra / n ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 3 : 5 1 . 5 2 . 4d e v r e s e ra / nw r 2 . 5 2 . 4n r e t t a p t s e t e v i e c e r e l b a n e d e l b a n e n r e t t a p t s e t e v i e c e r = 1 d e l b a n e t o n n r e t t a p t s e t e v i e c e r = 0 w r0 0 : 1 . 5 2 . 4t c e l e s n r e t t a p t s e t0 1 d e v r e s e r = 1 1 n r e t t a p t s e t y c n e u q e r f d e x i m = 0 1 n r e t t a p t s e t y c n e u q e r f w o l = 1 0 n r e t t a p t s e t y c n e u q e r f h g i h = 0 0 w r
52 register 4.49152 - phy_xs extended features register 4.49153 - phy_xs extended features notes : 1. rw = read/write, ro = read only. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 2 5 1 9 4 . 4k c a b p o o l m e t s y s i u a x e l b a n e t u o a t a d k c a b p o o l s x _ y h p n i n e h w t u o x t t a a t a d t i m s n a r t = 1 e d o m e d o m k c a b p o o l s x _ y h p n i n e h w s ' 1 l l a t i m s n a r t = 0 w r0 4 1 . 2 5 1 9 4 . 4k c a b p o o l m e t s y s i u a x e l b a n e ) h t a p x r > - x t ( k c a b p o o l i u a x e l b a n e = 1w r0 3 1 . 2 5 1 9 4 . 4e l b a n e s b r p i u a xs b r p e l b a n e = 1w r0 2 1 . 2 5 1 9 4 . 4r o t i n o m g o l a n a i u a x l o r t n o c t n i o p a t a d d e r e v o c e r 3 e n a l i u a x = 1 k c o l c d e r e v o c e r 3 e n a l i u a x = 0 8 : 1 1 . 2 5 1 9 4 . 4d e v r e s e ra / n 7 . 2 5 1 9 4 . 4d e k c o l 3 e n a lk c o l n i 3 e n a l = 1o ra / n 6 . 2 5 1 9 4 . 4d e k c o l 2 e n a lk c o l n i 2 e n a l = 1o ra / n 5 . 2 5 1 9 4 . 4d e k c o l 1 e n a lk c o l n i 1 e n a l = 1o ra / n 4 . 2 5 1 9 4 . 4d e k c o l 0 e n a lk c o l n i 0 e n a l = 1o ra / n 3 . 2 5 1 9 4 . 4d e k c o l l l p i u a xd e k c o l l l p i u a x = 1o ra / n 2 . 2 5 1 9 4 . 4e c n e r e f e r l a n r e t x e i u a x e d o m k c o l c k c o l c l a n r e t x e = 1 k c o l c e c n e r e f e r l a n r e t n i = 0 w r0 1 . 2 5 1 9 4 . 4t e s e r s x g x e v i e c e rt e s e r t o n = 1 t e s e r = 0 g n i r a e l c f l e s t o n : e t o n w r1 0 . 2 5 1 9 4 . 4t e s e r s x g x t i m s n a r tt e s e r t o n = 1 t e s e r = 0 g n i r a e l c f l e s t o n : e t o n w r1 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 3 5 1 9 4 . 4d e v r e s e ra / no r 7 . 3 5 1 9 4 . 4r o r r e s b r p 7 e n a l i u a xr o r r e = 1h l / o r 6 . 3 5 1 9 4 . 4r o r r e s b r p 6 e n a l i u a xr o r r e = 1h l / o r 5 . 3 5 1 9 4 . 4r o r r e s b r p 5 e n a l i u a xr o r r e = 1h l / o r 4 . 3 5 1 9 4 . 4r o r r e s b r p 4 e n a l i u a xr o r r e = 1h l / o r 3 . 3 5 1 9 4 . 4r o r r e s b r p 3 e n a l i u a xr o r r e = 1h l / o r- 2 . 3 5 1 9 4 . 4r o r r e s b r p 2 e n a l i u a xr o r r e = 1h l / o r- 1 . 3 5 1 9 4 . 4r o r r e s b r p 1 e n a l i u a xr o r r e = 1h l / o r- 0 . 3 5 1 9 4 . 4r o r r e s b r p 0 e n a l i u a xr o r r e = 1h l / o r-
53 register 4.49154 - phy_xs vendor specific register 4.49155 - phy_xs vendor specific register 4.49156 - phy_xs vendor specific register 4.49157 - phy_xs vendor specific notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared. 2. this bit is linked to an mdio latched high diagnostic alarm register bit. when either register is read, both bits will be cl eared. ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 1 : 5 1 . 4 5 1 9 4 . 4c i f i c e p s r o d n e vd e v r e s e ro r 9 . 4 5 1 9 4 . 4t s u j d a e t a r x t s x g x w o l f r e v o ) 2 . 8 6 8 6 3 . 1 o t d e k n i l ( w o l f r e v o = 1h l / o r2 e t o n 8 . 4 5 1 9 4 . 4t s u j d a e t a r x t s x g x w o l f r e d n u ) 2 . 8 6 8 6 3 . 1 o t d e k n i l ( w o l f r e d n u = 1h l / o r2 e t o n 7 . 4 5 1 9 4 . 4w o l f r e v o e t a r x r s x g x) 6 . 7 6 8 6 3 . 1 o t d e k n i l ( w o l f r e v o = 1h l / o r2 e t o n 6 . 4 5 1 9 4 . 4t s u j d a e t a r x r s x g x w o l f r e d n u ) 6 . 7 6 8 6 3 . 1 o t d e k n i l ( w o l f r e d n u = 1h l / o r2 e t o n 0 : 5 . 4 5 1 9 4 . 4c i f i c e p s r o d n e vd e v r e s e ro r- ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 2 1 : 5 1 . 5 5 1 9 4 . 4i u a x t e s f f o c n y s 3 l e n n a h c o r 8 : 1 1 . 5 5 1 9 4 . 4i u a x t e s f f o c n y s 2 l e n n a h c o r 4 : 7 . 5 5 1 9 4 . 4i u a x t e s f f o c n y s 1 l e n n a h c o r 0 : 3 . 5 5 1 9 4 . 4i u a x t e s f f o c n y s 0 l e n n a h c o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 2 1 : 5 1 . 6 5 1 9 4 . 4i u a x t e s f f o n g i l a 3 l e n n a h c o r 8 : 1 1 . 6 5 1 9 4 . 4i u a x t e s f f o n g i l a 2 l e n n a h c o r 4 : 7 . 6 5 1 9 4 . 4i u a x t e s f f o n g i l a 1 l e n n a h c o r 0 : 3 . 6 5 1 9 4 . 4i u a x t e s f f o n g i l a 0 l e n n a h c o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 5 1 . 7 5 1 9 4 . 43 r r e _ e s a h p s x _ y h pd a e r n o r a e l c , r o r r e e s a h p k c o l c 3 e n a l i u a xo r 4 1 . 7 5 1 9 4 . 42 r r e _ e s a h p s x _ y h pd a e r n o r a e l c , r o r r e e s a h p k c o l c 2 e n a l i u a xo r 3 1 . 7 5 1 9 4 . 41 r r e _ e s a h p s x _ y h pd a e r n o r a e l c , r o r r e e s a h p k c o l c 1 e n a l i u a xo r 2 1 . 7 5 1 9 4 . 40 r r e _ e s a h p s x _ y h pd a e r n o r a e l c , r o r r e e s a h p k c o l c 0 e n a l i u a xo r 0 : 1 1 . 7 5 1 9 4 . 4c i f i c e p s r o d n e vd e v r e s e ro r
54 register 4.49158 - phy_xs vendor specific register 4.49160 - phy_xs vendor specific ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 8 : 5 1 . 8 5 1 9 4 . 4c i f i c e p s r o d n e vd e v r e s e ro r 7 . 8 5 1 9 4 . 4e t y b r e p p u 3 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r 6 . 8 5 1 9 4 . 4e t y b r e p p u 2 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r 5 . 8 5 1 9 4 . 4e t y b r e p p u 1 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r 4 . 8 5 1 9 4 . 4e t y b r e p p u 0 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r 3 . 8 5 1 9 4 . 4e t y b r e w o l 3 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r 2 . 8 5 1 9 4 . 4e t y b r e w o l 2 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r 1 . 8 5 1 9 4 . 4e t y b r e w o l 1 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r 0 . 8 5 1 9 4 . 4e t y b r e w o l 0 e n a lr o r r e e d o c e d b 8 / b 0 1h l / o r ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 0 : 5 1 . 0 6 1 9 4 . 4e d o c e v i e c e r s x _ y h p r e t n u o c n o i t a l o i v d a e r n o r a e l c b s l = 0 t i b b s m = 5 1 t i b h t a p x t n i : e t o n r n / o r notes : 1. rw = read/write, ro = read only, lh = latch high, clear on read (note that if the condition exists following register read, t he bit will not be cleared, nr = non roll-over. xenpak digital optical monitoring (dom) overview the xenpak digital optical monitoring (dom) interface is a derivative of sff-8472: digital diagnostic monitoring interface for optical transceivers appropriate to xenpak transceivers. this specification defines a 256 byte block of register space that is accessible over the 2 wire serial mdio/mdc interface. a memory map is used to access measurements of transceiver temperature , receive optical power , laser output power , and laser bias current through the 2 wire serial mdio/mdc interface. support for these measurements is indicated through the capability registers (1.41065: dom capability and 1.41065: dom capability - extended). the transceiver generates this monitoring data by digitization of internal analog signals, which are calibrated to absolute measurements. measured parameters are reported in 16 bit data fields (two concatenated bytes). alarm flags are required so dom indicators can be made inputs to the link alarm status interrupt (lasi) function. calibrated alarm and warning threshold data is written during device manufacture.
55 xenpak digital optical monitoring mdio register space measured parameter definitions internally measured transceiver temperature this value is represented as a 16 bit signed twos complement value in increments of 1/256 degrees celsius between -40 c and +125 c. the HFCT-701XBD accuracy is better than +/- 5 c between 0 c and +70 c. table 15. temperature value laser bias current measured laser bias current in a. represented as a 16 bit unsigned integer with the current defined as the full 16 bit value (0 - 65535) with lsb equal to 2 a. total measurement range is from 0 ma to 655.35 ma. the HFCT-701XBD accuracy is better than +/- 10% of ibias set-point over the operating temperature and voltage range. table 16. current value (lsb = 2 a) e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e r 10 6 9 0 40 0 0 a9 9 9 0 47 2 0 as d l o h s e r h t g n i n r a w d n a m r a l a 16 5 0 1 40 6 0 a5 6 0 1 49 6 0 ae c a f r e t n i m o d e r u t a r e p m e te u l a v y r a n i be u l a v l a m i c e d a x e h e u l a vb s mb s lb s mb s l c 0 4 -0 0 0 1 1 0 1 10 0 0 0 0 0 0 08 d0 0 c 00 0 0 0 0 0 0 00 0 0 0 0 0 0 00 00 0 c 5 2 1 +1 0 1 1 1 1 1 00 0 0 0 0 0 0 0d 70 0 t n e r r u ce u l a v y r a n i be u l a v l a m i c e d a x e h e u l a vb s mb s lb s mb s l a m 0 . 00 0 0 0 0 0 0 00 0 0 0 0 0 0 00 00 0 a m 0 . 0 51 0 0 0 0 1 1 00 0 0 1 0 1 0 11 68 a a m 7 0 . 1 3 11 1 1 1 1 1 1 11 1 1 1 1 1 1 1f ff f
56 laser output power measured laser output power in mw. represented as a 16 bit unsigned integer with the power defined as the full 16 bit value (0 - 65535) with lsb equal to 0.1 w. total measurement range is from 0 mw to 6.5535 mw (-40 dbm to +8.2 dbm). data presented is average fiber coupled power and factory calibrated using the most representative fiber type. the HFCT-701XBD accuracy is +/- 2 db between -8.2 dbm and +1.5 dbm. the data is not valid when transmitter is disabled. table 17. tx power value receive optical power measured receive optical power in mw. this value is represented as a 16 bit unsigned integer with the power defined as the full 16 bit value (0 - 65535) with lsb equal to 0.1 w. the total measurement range is from 0 mw to 6.5535 mw (-40 dbm to +8.2 dbm). the data is average receive power from the fiber into the transceiver. the HFCT-701XBD accuracy is +/- 2db over average receive power range of -16 dbm to +2 dbm. table 18. rx power value table 18a. dom accuracy r e w o pe u l a v y r a n i be u l a v l a m i c e d a x e h e u l a vb s mb s lb s mb s l w m 0 . 00 0 0 0 0 0 0 00 0 0 0 0 0 0 00 00 0 w m 0 . 31 0 1 0 1 1 1 00 0 0 0 1 1 0 05 70 3 w m 5 3 5 5 . 61 1 1 1 1 1 1 11 1 1 1 1 1 1 1f ff f r e t e m a r a p) p y t ( n o i t a c i f i c e p s y c a r u c c a) x a m ( n o i t a c i f i c e p s y c a r u c c a e g n a r r e w o p x rb d 5 . 1 ) m b d 2 + o t m b d 6 1 - ( b d 0 . 2 ) m b d 2 + o t m b d 6 1 - ( e g n a r r e w o p t u p t u ob d 0 . 1 ) g v a m b d 5 . 0 + o t m b d 2 . 8 - ( b d 0 . 2 ) g v a m b d 5 . 0 + o t m b d 2 . 8 - ( e g n a r e r u t a r e p m e tc 2 ) c 5 7 + o t c 5 - ( c 5 ) c 5 7 + o t c 5 - ( e g n a r s a i b i a m 0 8 o t a m 2 % 0 1 ) a m 0 8 o t a m 2 ( r e w o pe u l a v y r a n i be u l a v l a m i c e d a x e h e u l a vb s mb s lb s mb s l w m 0 . 00 0 0 0 0 0 0 00 0 0 0 0 0 0 00 00 0 w m 0 . 11 1 1 0 0 1 0 00 0 0 0 1 0 0 07 20 1 w m 5 3 5 5 . 61 1 1 1 1 1 1 11 1 1 1 1 1 1 1f ff f
57 table 19. alarm and warning threshold memory map msb at low address each measured value has a corresponding high alarm, low alarm, high warning, and low warning threshold. these factory-preset values allow the user to determine when a particular value is outside of normal limits as programmed by agilent. e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e rt l u a f e d e u l a v g n i n a e m 10 6 9 0 40 0 0 a1 6 9 0 41 0 0 am r a l a h g i h p m e t r e v i e c s n a r tc 0 7 + 12 6 9 0 42 0 0 a3 6 9 0 43 0 0 am r a l a w o l p m e t r e v i e c s n a r tc 0 14 6 9 0 44 0 0 a5 6 9 0 45 0 0 ag n i n r a w h g i h p m e t r e v i e c s n a r tc 5 6 + 16 6 9 0 46 0 0 a7 6 9 0 47 0 0 ag n i n r a w w o l p m e t r e v i e c s n a r tc 5 + 18 6 9 0 48 0 0 a5 7 9 0 4f 0 0 ad e v r e s e r 16 7 9 0 40 1 0 a7 7 9 0 41 1 0 am r a l a h g i h t n e r r u c s a i b r e s a la m 0 8 18 7 9 0 42 1 0 a9 7 9 0 43 1 0 am r a l a w o l t n e r r u c s a i b r e s a la m 0 1 10 8 9 0 44 1 0 a1 8 9 0 45 1 0 ag n i n r a w h g i h t n e r r u c s a i b r e s a la m 5 7 12 8 9 0 46 1 0 a3 8 9 0 47 1 0 ag n i n r a w w o l t n e r r u c s a i b r e s a la m 5 1 14 8 9 0 48 1 0 a5 8 9 0 49 1 0 am r a l a h g i h r e w o p t u p t u o r e s a lm b d 0 . 2 + 16 8 9 0 4a 1 0 a7 8 9 0 4b 1 0 am r a l a w o l r e w o p t u p t u o r e s a lm b d 7 . 9 - 18 8 9 0 4c 1 0 a9 8 9 0 4d 1 0 ag n i n r a w h g i h r e w o p t u p t u o r e s a lm b d 0 . 1 + 10 9 9 0 4e 1 0 a1 9 9 0 4f 1 0 ag n i n r a w w o l r e w o p t u p t u o r e s a lm b d 0 . 4 - 12 9 9 0 40 2 0 a3 9 9 0 41 2 0 am r a l a h g i h r e w o p l a c i t p o e v i e c e rm b d 0 . 2 + 14 9 9 0 42 2 0 a5 9 9 0 43 2 0 am r a l a w o l r e w o p l a c i t p o e v i e c e rm b d 0 . 5 1 - 16 9 9 0 44 2 0 a7 9 9 0 45 2 0 ag n i n r a w h g i h r e w o p l a c i t p o e v i e c e rm b d 5 . 0 + 18 9 9 0 46 2 0 a9 9 9 0 47 2 0 ag n i n r a w w o l r e w o p l a c i t p o e v i e c e rm b d 0 . 2 1 - the values in these registers are represented as detailed in tables 15 to 18.
58 monitored a/d values supported measurements are calibrated to stated accuracies over vendor specified operating temperature and voltage and should be interpreted according to previous sections. dom status/control registers the following register has been reserved in the xenpak non-volatile register (nvr) space for digital optical monitoring (dom) capability. note: 1. ro = read only. table 20. monitored a/d value memory map e c i v e dm o r f l a m i c e dx e h o t l a m i c e dx e h e m a n r e t s i g e r 16 5 0 1 40 6 0 a7 5 0 1 41 6 0 ap m e t r e v i e c s n a r t 10 6 0 1 44 6 0 a1 6 0 1 45 6 0 at n e r r u c s a i b r e s a l 12 6 0 1 46 6 0 a3 6 0 1 47 6 0 ar e w o p t u p t u o r e s a l 14 6 0 1 48 6 0 a5 6 0 1 49 6 0 ar e w o p l a c i t p o e v i e c e r register 1.32890 ) s ( t i be m a nn o i t p i r c s e dw / r 1 e u l a v t l u a f e d 7 . 0 9 8 2 3 . 1s u t a t s: r e t s i g e r s u t a t s / l o r t n o c m o d d e t n e m e l p m i t o n = 0 d e t n e m e l p m i = 1 o r1 6 . 0 9 8 2 3 . 1t e s m o dd e t n e m e l p m i m o d n e h w t e so r1 5 . 0 9 8 2 3 . 1y t i l i b a p a c m d wt i b s i h t g n i t t e s : y t i l i b a p a c m o d e n a l y b e n a l m d w s i h t g n i t t e s . d i l a v e r a f f 0 a - o c 0 a s r e t s i g e r t a h t s e t a c i d n i f 6 0 a r e t s i g e r n i d e c a l p s n o i t a c i d n i e d i r r e v o t o n l l i w t i b ) y t i l i b a p a c m o d ( o r0 4 . 0 9 8 2 3 . 1e l a c s s a i b r e s a l: r o t c a f e l a c s s a i b r e s a l a 2 = 0 a 0 1 = 1 o r1 0 : 2 . 0 9 8 2 3 . 1m o d l a n r e t x ee c i v e d m o d l a n r e t x e f o s s e r d d ao r1 0 0
59 register 1.41071 digital optical monitoring (dom) capability - extended the optional dom control/status register 1.41216 provides facilities to update mdio registers with dom information: register 1.41216 optional digital optical monitoring (dom) control/status note: 1. ro = read only, rw = read/write ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 7 . 1 7 0 1 4 . 1e l b a p a c r o t i n o m p m e tg n i r o t i n o m e r u t a r e p m e t r e v i e c s n a r t e t a c i d n i o t t e s e l b a p a c o r1 6 . 1 7 0 1 4 . 1r o t i n o m s a i b r e s a l e l b a p a c e l b a p a c g n i r o t i n o m t n e r r u c s a i b r e s a l e t a c i d n i o t t e so r1 5 . 1 7 0 1 4 . 1e l b a p a c r o t i n o m p o le l b a p a c g n i r o t i n o m r e w o p t u p t u o r e s a l e t a c i d n i o t t e so r1 4 . 1 7 0 1 4 . 1r o t i n o m r e w o p x r e l b a p a c e l b a p a c g n i r o t i n o m r e w o p l a c i t p o e v i e c e r e t a c i d n i o t t e so r1 3 . 1 7 0 1 4 . 1s g a l f m r a l a d e t n e m e l p m i d e r o t i n o m r o f d e t n e m e l p m i s g a l f m r a l a e t a c i d n i o t t e s s e i t i t n a u q o r1 2 . 1 7 0 1 4 . 1s g a l f g n i n r a w d e t n e m e l p m i d e r o t i n o m r o f d e t n e m e l p m i s g a l f g n i n r a w e t a c i d n i o t t e s s e i t i t n a u q o r1 1 . 1 7 0 1 4 . 1e u r t = s t u p n i i s a li s a l o t s t u p n i e r a s e i t i t n a u q d e r o t i n o m e t a c i d n i o t t e s . e . i ( t e s e b o s l a t s u m 3 t i b , t e s s i t i b s i h t f i . n o i t c n u f . ) t r o p p u s g a l f m r a l a o r1 0 . 1 7 0 1 4 . 10 d e v r e s e ro r0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 2 : 3 . 6 1 2 1 4 . 1: s u t a t s d n a m m o c e l d i = 0 0 y l l u f s s e c c u s d e t e l p m o c d n a m m o c = 1 0 s r e t s i g e r o i d m s e t a c i d n i ( s s e r g o r p n i d n a m m o c = 0 1 a s m k a p n e x e e s - n o i t a m r o f n i m o d h t i w d e t a d p u g n i e b ) n o i t a m r o f n i l a n o i t i d d a r o f 9 1 e r u g i f d e l i a f d n a m m o c = 1 1 o r 0 : 1 . 6 1 2 1 4 . 1: s d n a m m o c e t a d p u o i d m f o e t a d p u e l g n i s a s e t a i t i n i s t i b o t e t i r w = 0 0 s i h t f o e t i r w . n o i t a m r o f n i m o d f o s e t y b l l a h t i w s r e t s i g e r . s e d o m e t a d p u c i d o i r e p s p o t s o s l a n o i t a n i b m o c t i b s r e t s i g e r o i d m f o e t a d p u c i d o i r e p c e s 1 = 1 0 s r e t s i g e r o i d m f o e t a d p u c i d o i r e p c e s 0 1 = 0 1 s r e t s i g e r o i d m f o e t a d p u c i d o i r e p c e s 0 6 = 1 1 w r0 0
60 notes regarding operation of dom control/status register update commands: implementation of control/status register for periodic update is vendor specific. the recommended operation is as follows: step 1. station management (sta) initiates periodic update: write to control bits 1.41216.1:0=[<0:1>,<1:0>,<1:1>]. step 2. mdio registers updated with all bytes of dom information: status bits =<1:0> during update. step 3. if update successful: - status bits =<0:1>. - sta capable of reading status bits between periodic updates of mdio registers. - mdio registers updated with all bytes of dom information at next scheduled interval: during update status bits =<1:0>, than are loaded with completion status (i.e. successful or failed). step 4. if update failed: - status bits =<1:1>. - periodic update of mdio registers stopped: sta capable of query through control/status bits. alarm and warning flags mdio registers 1.41072 to 1.41079 contain alarm and warning flags that monitor measured values in registers 1.41056-1.41069. two flag types are defined: ? alarm flags associated with transceiver temperature, receive optical power, laser output power, and laser bias current. alarm flags indicate conditions likely to be associated with an in- operational link and cause for immediate action. ? warning flags associated with transceiver temperature, receive optical power, laser output power, and laser bias current. warning flags indicate conditions outside the normally guaranteed bounds, but not necessarily causes of immediate link failures.
61 registers alarm and warning flag memory map note: 1. rw = read/write ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 7 . 2 7 0 1 4 . 1h g i h p m e t r e v i e c s n a r t m r a l a l e v e l m r a l a h g i h s d e e c x e p m e t r e v i e c s n a r t n e h w t e so r 6 . 2 7 0 1 4 . 1w o l p m e t r e v i e c s n a r t m r a l a l e v e l m r a l a w o l w o l e b s i p m e t r e v i e c s n a r t n e h w t e so r 5 - 4 . 2 7 0 1 4 . 1d e v r e s e r 3 . 2 7 0 1 4 . 1h g i h t n e r r u c s a i b r e s a l m r a l a l e v e l m r a l a h g i h s d e e c x e t n e r r u c s a i b r e s a l n e h w t e so r 2 . 2 7 0 1 4 . 1w o l t n e r r u c s a i b r e s a l m r a l a l e v e l m r a l a w o l w o l e b s i t n e r r u c s a i b r e s a l n e h w t e so r 1 . 2 7 0 1 4 . 1r e w o p t u p t u o r e s a l m r a l a h g i h l e v e l m r a l a h g i h s d e e c x e r e w o p t u p t u o r e s a l n e h w t e so r 0 . 2 7 0 1 4 . 1r e w o p t u p t u o r e s a l m r a l a w o l l e v e l m r a l a w o l w o l e b s i r e w o p t u p t u o r e s a l n e h w t e so r 7 . 3 7 0 1 4 . 1r e w o p l a c i t p o e v i e c e r m r a l a h g i h l e v e l m r a l a h g i h s d e e c x e r e w o p l a c i t p o e v i e c e r n e h w t e so r 6 . 3 7 0 1 4 . 1r e w o p l a c i t p o e v i e c e r g n i n r a w w o l g n i n r a w w o l w o l e b s i r e w o p l a c i t p o e v i e c e r n e h w t e s l e v e l o r 5 - 0 . 3 7 0 1 4 . 1d e v r e s e r 1 : 7 . 5 7 - 4 7 0 1 4 . 1d e v r e s e r 7 . 6 7 0 1 4 . 1h g i h p m e t r e v i e c s n a r t g n i n r a w l e v e l g n i n r a w h g i h s d e e c x e p m e t r e v i e c s n a r t n e h w t e so r 6 . 6 7 0 1 4 . 1h g i h w o l r e v i e c s n a r t g n i n r a w l e v e l g n i n r a w w o l w o l e b s i p m e t r e v i e c s n a r t n e h w t e so r 5 - 4 . 6 7 0 1 4 . 1d e v r e s e r 3 . 6 7 0 1 4 . 1h g i h t n e r r u c s a i b r e s a l g n i n r a w l e v e l g n i n r a w h g i h s d e e c x e t n e r r u c s a i b r e s a l n e h w t e so r 2 . 6 7 0 1 4 . 1w o l t n e r r u c s a i b r e s a l g n i n r a w l e v e l g n i n r a w w o l w o l e b s i t n e r r u c s a i b r e s a l n e h w t e so r 1 . 6 7 0 1 4 . 1r e w o p t u p t u o r e s a l g n i n r a w h g i h l e v e l g n i n r a w h g i h s d e e c x e r e w o p t u p t u o r e s a l n e h w t e so r 0 . 6 7 0 1 4 . 1r e w o p t u p t u o r e s a l g n i n r a w w o l l e v e l g n i n r a w w o l w o l e b s i r e w o p t u p t u o r e s a l n e h w t e so r 7 . 7 7 0 1 4 . 1r e w o p l a c i t p o e v i e c e r g n i n r a w h g i h g n i n r a w h g i h s d e e c x e r e w o p l a c i t p o e v i e c e r n e h w t e s l e v e l o r 6 . 7 7 0 1 4 . 1r e w o p l a c i t p o e v i e c e r g n i n r a w w o l g n i n r a w w o l w o l e b s i r e w o p l a c i t p o e v i e c e r n e h w t e s l e v e l o r 5 - 0 . 7 7 0 1 4 . 1d e v r e s e r 0 : 7 . 9 - 8 7 0 1 4 . 1d e v r e s e r
62 operation a top-level block diagram of digital optical monitoring (dom) incorporated into the link alarm status interrupt (lasi) function is shown in figure 20. tx_flag status assertion of tx_flag indicates that one or more of the transmitter operating parameters (transceiver temperature, laser bias current, or laser output power) exceeds the alarm levels. tx alarm flags only monitor a/d values in registers 1.41056-1.41069. tx_flag shall be the logic or of the bits in register 1.41072. the contents of the tx_flag status register are shown below. bit 1 of tx_alarm (tx_flag) will have the properties of latch high, clear on read (note that if the condition exists following register read, the bit will not be cleared). tx alarm flags 1.41072 tx flag control 1.36870 rx alarm flags 1.41073 tx flag control 1.36870 tx_flag to bit 1 of tx_alarm rx_flag to bit 1 of rx_alarm figure 20. dom/lasi block diagram register 1.41072 tx_flag status bits notes: 1. o = optional, ro = read only (this register may be optionally implemented as read/write). ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 7 . 2 7 0 1 4 . 1h g i h p m e tm r a l a h g i h e r u t a r e p m e t r e v i e c s n a r to r / o 6 . 2 7 0 1 4 . 1w o l p m e tm r a l a w o l e r u t a r e p m e t r e v i e c s n a r to r / o 4 : 5 . 2 7 0 1 4 . 1d e v r e s e ro r 3 . 2 7 0 1 4 . 1h g i h t n e r r u cm r a l a h g i h t n e r r u c s a i b r e s a lo r / o 2 . 2 7 0 1 4 . 1w o l t n e r u cm r a l a w o l t n e r r u c s a i b r e s a lo r / o 1 . 2 7 0 1 4 . 1h g i h p o lm r a l a h g i h r e w o p t u p t u o r e s a lo r / o 0 . 2 7 0 1 4 . 1w o l p o lm r a l a w o l r e w o p t u p t u o r e s a lo r / o
63 tx_flag control tx_flag may be programmed to assert only when specific transmit operation parameters exceed their alarm levels. the programming is performed by writing the contents of a mask register located at offset 1.36870. the contents of register 1.41072 shall be anded with the contents of register 1.36870 prior to application of the or function that generates the tx_flag signal. register 1.36870: tx_flag control bits rx_flag status assertion of rx_flag indicates that one or more of the receiver operating parameters (receive optical power) exceeds the alarm levels. rx alarm flags only monitor a/d values in registers 1.41056-1.41070. rx_flag shall be the logic or of the bits in register 1.41073. the contents of the rx_flag status register are shown below. bit 1 of rx_alarm (rx_flag) will have the properties of latch high, clear on read (note that if the condition exists following register read, the bit will not be cleared). register 1.41073: rx_flag status bits rx_flag control rx_flag may be programmed to assert only when specific receive operation parameters exceed their alarm levels. the programming is performed by writing the contents of a mask register located at offset 1.36871. the contents of register 1.41072 shall be anded with the contents of register 1.36871 prior to application of the or function that generates the rx_flag signal. register 1.36871: rx_flag control bits note: 1. rw = read/write, o = optional, ro = read only (this register may be optionally implemeted as read/write). ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 7 . 0 7 8 6 3 . 1e l b a n e h g i h p m e te l b a n e m r a l a h g i h p m e t r e v i e c s n a r tw r0 6 . 0 7 8 6 3 . 1e l b a n e w o l p m e te l b a n e m r a l a w o l p m e t r e v i e c s n a r tw r0 4 : 5 . 0 7 8 6 3 . 1d e v r e s e rw r0 3 . 0 7 8 6 3 . 1e l b a n e h g i h t n e r r u ce l b a n e m r a l a h g i h t n e r r u c s a i b r e s a lw r0 2 . 0 7 8 6 3 . 1e l b a n e w o l t n e r r u ce l b a n e m r a l a w o l t n e r r u c s a i b r e s a lw r0 1 . 0 7 8 6 3 . 1e l b a n e h g i h p o le l b a n e m r a l a h g i h r e w o p t u p t u o r e s a lw r0 0 . 0 7 8 6 3 . 1e l b a n e w o l p o le l b a n e m r a l a w o l r e w o p t u p t u o r e s a lw r0 ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 7 . 3 7 0 1 4 . 1h g i h r e w o p x rm r a l a h g i h r e w o p l a c i t p o e v i e c e ro r / o 6 . 3 7 0 1 4 . 1w o l r e w o p x rm r a l a w o l r e w o p l a c i t p o e v i e c e ro r / o 0 : 5 . 3 7 0 1 4 . 1d e v r e s e ro r ) s ( t i be m a nn o i t p i r c s e dw / r 1 ) c e d ( e u l a v t l u a f e d 7 . 1 7 8 6 3 . 1e l b a n e h g i h r e w o p x re l b a n e m r a l a h g i h r e w o p l a c i t p o e v i e c e rw r0 6 . 1 7 8 6 3 . 1e l b a n e w o l r e w o p x re l b a n e m r a l a w o l r e w o p l a c i t p o e v i e c e rw r0 0 : 5 . 1 7 8 6 3 . 1d e v r e s e rw r0
regulatory compliance the HFCT-701XBD is intended to enable commercial system designers to develop equipment that complies with the various regulations governing certification of information technology equipment (see table 15). electrostatic discharge (esd) there are two design cases in which immunity to esd damage is important. the first case is during handling of the transceiver prior to plugging into the circuit board. it is important to use normal esd handling precautions for esd sensitive devices. these precautions include using grounded wrist straps, work benches and floor mats in esd controlled areas. the second case to consider is static charges to the exterior of the equipment chassis containing the transceiver parts. to the extent that the sc duplex connector is exposed to the outside of the equipment chassis it may be subject to whatever esd system level criteria that the equipment is intended to meet. electromagnetic interference (emi) most equipment design utilizing these high speed transceivers from agilent will be required to meet the requirements of fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. performance of the hfct- 701xbd transceiver is dependent upon customer board and chassis design. immunity equipment utilizing these transceivers will be subject to radio frequency electromagnetic fields in some environments. these transceivers have been characterized without the benefit of the normal equipment chassis enclosure and results are reported below. performance of a system containing these transceivers within a well-designed chassis enclosure is expected to be better than the results of these tests without a chassis enclosure. glossary phy = module = used interchangeably with hfct- 701xb in this document. network = used to indicate elements that are on the optical side of the module. network loopback = a signal path within the module from the optical input of the module to the optical output of the module. system = used to indicate elements that are on the electrical side of the module. system loopback = a signal path within the module from the electrical input of the module to the electrical output of the module.
www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6271 2451 india, australia, new zealand: (+65) 6271 2394 japan: (+81 3) 3335-8152(domestic/inter- national), or 0120-61-1280(domestic only) korea: (+65) 6271 2194 malaysia, singapore: (+65) 6271 2054 taiwan: (+65) 6271 2654 data subject to change. copyright ? 2004 agilent technologies, inc. march 11, 2004 5989-0765en table 19. regulatory compliance - typical performance e r u t a e fd o h t e m t s e te c n a m r o f r e p l a r e n e ge r o c - 8 6 4 - r g a i d r o c l e t s t n e m e r i u q e r l a n i m r e t e t o m e r h t i w e c n a d r o c c a n i d e i f i l a u q y d o b n a m u h - e g r a h c s i d c i t a t s o r t c e l e l e d o m 5 1 0 3 d o h t e m 3 8 8 d t s l i mv 0 0 5 e c i v e d d e g r a h c - e g r a h c s i d c i t a t s o r t c e l e l e d o m 1 0 1 c - 2 2 d s e j c e d e jv 0 0 5 e g r a h c s i d t c a t n o c - e g r a h c s i d c i t a t s o r t c e l e2 - 4 - 0 0 0 1 6 c e iv 0 0 0 8 e c n e r e f r e t n i c i t e n g a m o r t c e l e b s s a l c 2 2 0 5 5 n e c e l e n e c b s s a l c c c f 2 s s a l c i c c v ) b 2 2 r p s i c ( s i s s a h c d n a d r a o b r e m o t s u c n o t n a d n e p e d e r a s n i g r a m n g i s e d y t i n u m m i3 - 4 - 0 0 0 1 6 c e i f o n o i t a i r a v m / v 0 1 a m o r f d e v r e s b o s a w 2 1 - e 1 n a h t r e t t e b f o r e b a . z h g 1 o t z h m 7 2 m o r f t p e w s d l e i f y t e f a s e y e1 s s a l c h r d c / 5 2 8 0 6 c e i1 5 - 0 2 2 1 2 5 9 : h r d c 1 0 / 0 3 2 0 1 5 / 3 3 9 : v u t

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